公开(公告)号：WO2015126575A3

公开(公告)日：2015-10-29

申请号：PCT/US2015012975

申请日：2015-01-27

Applicant: GEN ELECTRIC

Inventor： MCMAHON JAMES JAY ,  STEVANOVIC LJUBISA DRAGOLJUB ,  ARTHUR STEPHEN DALEY ,  GROCZYCA THOMAS BERT ,  BEAUPRE RICHARD ALFRED ,  STUM ZACHARY MATTHEW ,  BOLOTNIKOV ALEXANDER VIKTOROVICH

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L21/045 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.

Abstract translation: 介绍了一种半导体器件。 该器件包括含有碳化硅的半导体层，并具有第一表面和第二表面。 栅绝缘层设置在半导体层的第一表面的一部分上，栅电极设置在栅绝缘层上。 该器件还包括设置在栅极绝缘层和栅电极之间的邻近栅电极的边缘的拐角处的氧化物，从而栅极绝缘层在拐角处具有比该层的中心处的厚度更大的厚度。 还提供了用于制造该装置的方法。

公开(公告)号：WO2015126575A8

公开(公告)日：2016-08-18

申请号：PCT/US2015012975

申请日：2015-01-27

Applicant: GEN ELECTRIC

Inventor： MCMAHON JAMES JAY ,  STEVANOVIC LJUBISA DRAGOLJUB ,  ARTHUR STEPHEN DALEY ,  GORCZYCA THOMAS BERT ,  BEAUPRE RICHARD ALFRED ,  STUM ZACHARY MATTHEW ,  BOLOTNIKOV ALEXANDER VIKTOROVICH

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L21/045 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.

Abstract translation: 介绍了半导体器件。 该器件包括具有碳化硅的半导体层，并具有第一表面和第二表面。 栅极绝缘层设置在半导体层的第一表面的一部分上，栅电极设置在栅极绝缘层上。 该器件还包括设置在栅极绝缘层和栅电极之间的邻近栅电极的边缘的角部处的氧化物，因此栅极绝缘层在角部具有比层的中心处的厚度更大的厚度。 还提供了一种用于制造该装置的方法。

公开(公告)号：JP2003265465A

公开(公告)日：2003-09-24

申请号：JP2003050274

申请日：2003-02-27

Applicant: GEN ELECTRIC

Inventor： STEVANOVIC LJUBISA DRAGOLJUB ,  OLCZAK EUGENE GEORGE ,  MUELLER FRANK JACOB JOHN ,  SUNDERMANN DIETMAR KARL

IPC: G21K5/00 ,  A61B6/08 ,  A61N5/10 ,  F21V7/00 ,  F21Y101/00 ,  G03B42/08 ,  G21K5/02

Abstract: PROBLEM TO BE SOLVED: To perform visible marking for a target region to be exposed with X-ray. SOLUTION: This X-ray collimator light system includes a long life X-ray collimator light source 10, an optical concentrator 11 situated at a first focal spot and configured for concentrating X-ray collimator light from the light source to a second focal spot, and an opaque shield 14 having an aperture 16 therein situated proximate to the second focal spot and being of such a geometrical shape so as to maximize light throughput while meeting light field edge contrast requirement. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2000092856A

公开(公告)日：2000-03-31

申请号：JP24683699

申请日：1999-09-01

Applicant: GEN ELECTRIC

Inventor： STEIGERWALD ROBERT L ,  WIRTH WILLIAM FREDERIC ,  STEVANOVIC LJUBISA DRAGOLJUB ,  PARK JOHN N

IPC: H03F3/217 ,  H02M7/48 ,  H02M7/5387

Abstract: PROBLEM TO BE SOLVED: To provide a switching amplifier apparatus for generating optional continuous waveform which is suitable for driving a gradient coil of a magneto- resonance imaging(MRI) apparatus. SOLUTION: A partial voltage back regulator (66) controls a high voltage bus for a total bridge circuit (52) in order to reduce total switching loss and distribute such switching loss. When a high output voltage is required and when low voltage devices (60, 62) of back regulator are switched to the PWM (Pulse Width Modulation) system and a low output voltage is required, a high voltage device of bridge is switched to the PWM system. The optimum performance for a predetermined magneto-resonance image sequence can be attained by regulating an input bus voltage with the variable input power supply (55) which may be operated in the high power factor mode.

公开(公告)号：AU2009238359A1

公开(公告)日：2011-06-09

申请号：AU2009238359

申请日：2009-11-20

Applicant: GEN ELECTRIC

Inventor： STEVANOVIC LJUBISA DRAGOLJUB ,  YAN LE ,  SOLOVITZ STEPHEN ADAM ,  BALASUBRAMANIAM MADADEVAN ,  BEAUPRE RICHARD ALFRED ,  ZHANG RICHARD S ,  GUNTURI SATISH SIVARAMA ,  PAUTSCH ADAM GREGORY ,  MALLINA RAMAKRISHNA VENKATA

IPC: H05K7/20 ,  F28F13/00 ,  H01L23/367

公开(公告)号：CA2695746A1

公开(公告)日：2010-09-09

申请号：CA2695746

申请日：2010-03-04

Applicant: GEN ELECTRIC

Inventor： BEAUPRE RICHARD ALFRED ,  STEVANOVIC LJUBISA DRAGOLJUB

IPC: H01L23/46 ,  B32B18/00 ,  G12B15/00 ,  H05K7/20

Abstract: A substrate (12) for power electronics (100) mounted thereon, comprises a middle ceramic layer (120) having a lower surface (124) and an upper surface (123), an upper metal layer (121) attached to the upper surface (124) of the middle ceramic layer (120), and a lower metal layer (122) attached to the lower surface (124) of the middle ceramic layer (120). The lower metal layer (122) has a plurality of millichannels (125, 126) configured to deliver a coolant for cooling the power electronics (100), wherein the millichannels (125, 126) are formed on the lower metal layer (122) prior to attachment to the lower surface (124) of the middle ceramic layer (120). Methods for making a cooling device and an apparatus (10) are also presented.

公开(公告)号：CA2687936A1

公开(公告)日：2010-06-22

申请号：CA2687936

申请日：2009-12-10

Applicant: GEN ELECTRIC

Inventor： BEAUPRE RICHARD ALFRED ,  STEVANOVIC LJUBISA DRAGOLJUB ,  ERNO DANIEL JASON ,  WOYCHIK CHARLES GERARD

IPC: F28D1/03 ,  B32B15/04 ,  B32B18/00 ,  F28F3/12 ,  F28F21/04 ,  H01L23/34

Abstract: A cooling device (10) includes a ceramic substrate (16) with a metal layer (22) bonded to an outer planar surface (18). The cooling device (10) also includes a channel layer (24) bonded to an opposite side of the ceramic substrate (16) and a manifold layer (26) bonded to an outer surface (28) of the channel layer (24). The substrate layers (16), (22), (24), (26) are bonded together using a high temperature process such as brazing to form a single substrate assembly (14). A plenum housing (30) is bonded to the single substrate assembly (14) via a low temperature bonding process such as adhesive bonding and is configured to provide extended manifold layer inlet and outlet ports (32), (34).

公开(公告)号：CA2589183A1

公开(公告)日：2007-01-04

申请号：CA2589183

申请日：2005-11-14

Applicant: GEN ELECTRIC

Inventor： STEVANOVIC LJUBISA DRAGOLJUB ,  SOLOVITZ STEPHEN ADAM

IPC: H05K7/20 ,  H01L23/00

Abstract: An apparatus for cooling at least one heated surface includes a base plate defining a number of inlet and outlet manifolds. The inlet manifolds are configured to receive a coolant, and the outlet manifolds exhaust the coolant. The inlet and outlet manifolds are interleaved. The apparatus also includes at least one substrate having inner and outer surfaces. The inner surface is coupled to the base plate and defines a number of microchannels that receive the coolant from the inlet manifolds and deliver the coolant to the outlet manifolds. The microchannels are oriented substantially perpendicular to the inlet and outlet manifolds. The outer surface is in thermal contact with the heated surface. The apparatus also includes an inlet plenum that supplies the coolant to the inlet manifolds, and an outlet plenum that exhausts the coolant from the outlet manifolds. The inlet plenum and outlet plenum are oriented in a plane of the base plate.

公开(公告)号：CA2687936C

公开(公告)日：2017-12-05

申请号：CA2687936

申请日：2009-12-10

Applicant: GEN ELECTRIC

Inventor： BEAUPRE RICHARD ALFRED ,  STEVANOVIC LJUBISA DRAGOLJUB ,  ERNO DANIEL JASON ,  WOYCHIK CHARLES GERARD

IPC: F28D1/03 ,  B32B15/04 ,  B32B18/00 ,  F28F3/12 ,  F28F21/04 ,  H01L23/34

Abstract: A cooling device (10) includes a ceramic substrate (16) with a metal layer (22) bonded to an outer planar surface (18). The cooling device (10) also includes a channel layer (24) bonded to an opposite side of the ceramic substrate (16) and a manifold layer (26) bonded to an outer surface (28) of the channel layer (24). The substrate layers (16), (22), (24), (26) are bonded together using a high temperature process such as brazing to form a single substrate assembly (14). A plenum housing (30) is bonded to the single substrate assembly (14) via a low temperature bonding process such as adhesive bonding and is configured to provide extended manifold layer inlet and outlet ports (32), (34).

公开(公告)号：GB2470991A

公开(公告)日：2010-12-15

申请号：GB201008668

申请日：2010-05-25

Applicant: GEN ELECTRIC

Inventor： BEAUPRE RICHARD ALFRED ,  STEVANOVIC LJUBISA DRAGOLJUB ,  BRUNNER DIETER GERHARD

IPC: H01L23/373 ,  H01L23/473 ,  H05K7/20

Abstract: A heatsink assembly 10 for cooling a heated device 50 includes an electrically isolating layer 64 such as a ceramic substrate having a plurality of cooling fluid channels 26 integrated therein. The electrically isolating layer 64 includes a topside surface 66 and a bottomside surface 68. A layer of electrically conducting material 62 is bonded or brazed either to the topside or the bottomside surfaces 66, 68 of the electrically isolating layer 64. The electrically conducting material 62 and the electrically isolating layer 64 have substantially identical coefficients of thermal expansion. Preferably the fluid cooling consists of inlet and outlet plena (20, fig 2), inlet and outlet manifolds (16,18, fig 2) connected to the plena, and cooling fluid channels 26, of micro-channel to milli-channel dimensions in the electrically isolating layer 64 . The electrically isolating layer 64 preferably consists of a ceramic such as AIN, BeO, Si3N4and A12O3. The cooling channels in the electrically isolating layer may be arranged to be continuous or in the form of discreet arrays as shown in fig 5.