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1.发明申请
公开(公告)号：WO2015126575A3
公开(公告)日：2015-10-29
申请号：PCT/US2015012975
申请日：2015-01-27
Applicant: GEN ELECTRIC
Inventor： MCMAHON JAMES JAY , STEVANOVIC LJUBISA DRAGOLJUB , ARTHUR STEPHEN DALEY , GROCZYCA THOMAS BERT , BEAUPRE RICHARD ALFRED , STUM ZACHARY MATTHEW , BOLOTNIKOV ALEXANDER VIKTOROVICH
IPC: H01L29/78 , H01L21/336 , H01L29/423
CPC classification number: H01L29/7802 , H01L21/045 , H01L21/049 , H01L29/1608 , H01L29/42368 , H01L29/66068
Abstract: A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.
Abstract translation: 介绍了一种半导体器件。 该器件包括含有碳化硅的半导体层，并具有第一表面和第二表面。 栅绝缘层设置在半导体层的第一表面的一部分上，栅电极设置在栅绝缘层上。 该器件还包括设置在栅极绝缘层和栅电极之间的邻近栅电极的边缘的拐角处的氧化物，从而栅极绝缘层在拐角处具有比该层的中心处的厚度更大的厚度。 还提供了用于制造该装置的方法。
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2.发明申请
公开(公告)号：WO2015126575A8
公开(公告)日：2016-08-18
申请号：PCT/US2015012975
申请日：2015-01-27
Applicant: GEN ELECTRIC
Inventor： MCMAHON JAMES JAY , STEVANOVIC LJUBISA DRAGOLJUB , ARTHUR STEPHEN DALEY , GORCZYCA THOMAS BERT , BEAUPRE RICHARD ALFRED , STUM ZACHARY MATTHEW , BOLOTNIKOV ALEXANDER VIKTOROVICH
IPC: H01L29/78 , H01L21/336 , H01L29/423
CPC classification number: H01L29/7802 , H01L21/045 , H01L21/049 , H01L29/1608 , H01L29/42368 , H01L29/66068
Abstract: A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.
Abstract translation: 介绍了半导体器件。 该器件包括具有碳化硅的半导体层，并具有第一表面和第二表面。 栅极绝缘层设置在半导体层的第一表面的一部分上，栅电极设置在栅极绝缘层上。 该器件还包括设置在栅极绝缘层和栅电极之间的邻近栅电极的边缘的角部处的氧化物，因此栅极绝缘层在角部具有比层的中心处的厚度更大的厚度。 还提供了一种用于制造该装置的方法。
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公开(公告)号：SG182076A1
公开(公告)日：2012-07-30
申请号：SG2011090644
申请日：2011-12-07
Applicant: GEN ELECTRIC
Inventor： BEAUPRE RICHARD ALFRED , MCCONNELEE PAUL ALAN , GOWDA ARUN VIRUPAKSHA , GORCZYCA THOMAS BERT
Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.Figure 1
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4.发明专利
公开(公告)号：CA2695746C
公开(公告)日：2011-11-08
申请号：CA2695746
申请日：2010-03-04
Applicant: GEN ELECTRIC
Inventor： BEAUPRE RICHARD ALFRED , STEVANOVIC LJUBISA DRAGOLJUB
Abstract: A substrate (12) for power electronics (100) mounted thereon, comprises a middle ceramic layer (120) having a lower surface (124) and an upper surface (123), an upper metal layer (121) attached to the upper surface (124) of the middle ceramic layer (120), and a lower metal layer (122) attached to the lower surface (124) of the middle ceramic layer (120). The lower metal layer (122) has a plurality of millichannels (125, 126) configured to deliver a coolant for cooling the power electronics (100), wherein the millichannels (125, 126) are formed on the lower metal layer (122) prior to attachment to the lower surface (124) of the middle ceramic layer (120). Methods for making a cooling device and an apparatus (10) are also presented.
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公开(公告)号：CA2563480C
公开(公告)日：2016-02-02
申请号：CA2563480
申请日：2006-10-12
Applicant: GEN ELECTRIC
Inventor： DELGADO ELADIO CLEMENTE , BEAUPRE RICHARD ALFRED
Abstract: A power circuit package (10) includes a base (12) including a substrate (14), a plurality of interconnect circuit layers (16) over the substrate with each including a substrate insulating layer (18) patterned with substrate electrical interconnects (20), and via connections (22, 24) extending from a top surface of the substrate to at least one of the substrate electrical interconnects (20); and a power semiconductor module (26) including power semiconductor devices (28) each including device pads (30) on a top surface of the respective power semiconductor device and backside contacts (31) on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure (32), the membrane structure including a membrane insulating layer (34) and membrane electrical interconnects (36) over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts (31) are coupled to selected substrate electrical interconnects or via connections.
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Patent Agency Ranking
公开(公告)号：CA2768534A1
公开(公告)日：2012-08-28
申请号：CA2768534
申请日：2012-02-16
Applicant: GEN ELECTRIC
Inventor： BEAUPRE RICHARD ALFRED , SMOLENSKI JOSEPH LUCIAN
Abstract: A busbar (10) for power conversion applications that includes two planar conductors (20, 30) that have terminal locations (22, 32); a first planar insulator (40) located between the planar conductors (20, 30); two impedances elements (24, 34) that are electrically connected to each of the planar conductors (20, 30), wherein the impedance elements (24, 34) each extend in a plane that is non-coplanar from the planar conductors (20, 30), further wherein the impedance elements (24, 34) are configured so as to define a gap (50) between them; and a second planar insulator (45) is located in the gap (50). The present invention has been described in terms of specific embodiment(s), and it is recognized that equivalents, alternatives, and modifications, aside from those expressly stated, are possible and within the scope of the appending claims.
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公开(公告)号：AU2009238359A1
公开(公告)日：2011-06-09
申请号：AU2009238359
申请日：2009-11-20
Applicant: GEN ELECTRIC
Inventor： STEVANOVIC LJUBISA DRAGOLJUB , YAN LE , SOLOVITZ STEPHEN ADAM , BALASUBRAMANIAM MADADEVAN , BEAUPRE RICHARD ALFRED , ZHANG RICHARD S , GUNTURI SATISH SIVARAMA , PAUTSCH ADAM GREGORY , MALLINA RAMAKRISHNA VENKATA
IPC: H05K7/20 , F28F13/00 , H01L23/367
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8.发明专利
公开(公告)号：CA2695746A1
公开(公告)日：2010-09-09
申请号：CA2695746
申请日：2010-03-04
Applicant: GEN ELECTRIC
Inventor： BEAUPRE RICHARD ALFRED , STEVANOVIC LJUBISA DRAGOLJUB
Abstract: A substrate (12) for power electronics (100) mounted thereon, comprises a middle ceramic layer (120) having a lower surface (124) and an upper surface (123), an upper metal layer (121) attached to the upper surface (124) of the middle ceramic layer (120), and a lower metal layer (122) attached to the lower surface (124) of the middle ceramic layer (120). The lower metal layer (122) has a plurality of millichannels (125, 126) configured to deliver a coolant for cooling the power electronics (100), wherein the millichannels (125, 126) are formed on the lower metal layer (122) prior to attachment to the lower surface (124) of the middle ceramic layer (120). Methods for making a cooling device and an apparatus (10) are also presented.
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公开(公告)号：CA2687936A1
公开(公告)日：2010-06-22
申请号：CA2687936
申请日：2009-12-10
Applicant: GEN ELECTRIC
Inventor： BEAUPRE RICHARD ALFRED , STEVANOVIC LJUBISA DRAGOLJUB , ERNO DANIEL JASON , WOYCHIK CHARLES GERARD
Abstract: A cooling device (10) includes a ceramic substrate (16) with a metal layer (22) bonded to an outer planar surface (18). The cooling device (10) also includes a channel layer (24) bonded to an opposite side of the ceramic substrate (16) and a manifold layer (26) bonded to an outer surface (28) of the channel layer (24). The substrate layers (16), (22), (24), (26) are bonded together using a high temperature process such as brazing to form a single substrate assembly (14). A plenum housing (30) is bonded to the single substrate assembly (14) via a low temperature bonding process such as adhesive bonding and is configured to provide extended manifold layer inlet and outlet ports (32), (34).
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公开(公告)号：CA2555394C
公开(公告)日：2016-02-23
申请号：CA2555394
申请日：2006-08-03
Applicant: GEN ELECTRIC
Inventor： FILLION RAYMOND ALBERT , BEAUPRE RICHARD ALFRED , ELASSER AHMED , WOJNAROWKSI ROBERT JOHN , KORMAN CHARLES STEVEN
IPC: H01L23/02 , H01L21/70 , H01L21/768 , H01L23/055 , H01L23/48
Abstract: A semiconductor chip packaging structure comprising a dielectric film 10 having one or more through holes 11 aligned with the one or more contact pads 22 and 23 of at least one power semiconductor chip 21. A patterned electrically conductive layer 40 adjacent to the dielectric film 10 has one or more electrically conductive posts 41 which extend through the one or more though holes 11 aligned with the contact pads 22 and 23 to electrically couple the conductive layer 40 to the contact pads 22 and 23. In certain embodiments, one or more air gaps 91 may be formed between the dielectric film 10 and the active surface 24 of the at least one power semiconductor chip 21. Methods for fabricating the semiconductor chip packaging structure are also disclosed.
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