公开(公告)号：US20210265198A1

公开(公告)日：2021-08-26

申请号：US16800011

申请日：2020-02-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Henry L. Aldridge, JR. ,  Johnatan A. Kantarovsky ,  Jeonghyun Hwang

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/06

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure.

公开(公告)号：US20240105595A1

公开(公告)日：2024-03-28

申请号：US17934389

申请日：2022-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Santosh Sharma ,  Michael J. Zierak ,  Steven J. Bentley ,  Ephrem G. Gebreselasie

IPC: H01L23/525 ,  H01L21/76 ,  H01L27/06 ,  H01L29/20

CPC classification number: H01L23/5256 ,  H01L21/7605 ,  H01L27/0605 ,  H01L29/2003

Abstract: Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.

公开(公告)号：US11881506B2

公开(公告)日：2024-01-23

申请号：US17386062

申请日：2021-07-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Brett T. Cucci ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/823481 ,  H01L29/66431 ,  H01L29/7786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

公开(公告)号：US20230139011A1

公开(公告)日：2023-05-04

申请号：US17517738

申请日：2021-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhong-Xiang He ,  Jeonghyun Hwang ,  Ramsey M. Hazbun ,  Brett T. Cucci ,  Ajay Raman ,  Johnatan A. Kantarovsky

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

公开(公告)号：US20220375871A1

公开(公告)日：2022-11-24

申请号：US17323423

申请日：2021-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sunil K. Singh ,  Vibhor Jain ,  Siva P. Adusumilli ,  Sebastian T. Ventrone ,  Johnatan A. Kantarovsky ,  Yves T. Ngu

IPC: H01L23/544 ,  H01L23/48 ,  G01N21/64

Abstract: The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

公开(公告)号：US11380759B2

公开(公告)日：2022-07-05

申请号：US16939213

申请日：2020-07-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma Rana ,  Anthony K. Stamper ,  Johnatan A. Kantarovsky ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/763 ,  H01L21/8234 ,  H01L29/10

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US20220165676A1

公开(公告)日：2022-05-26

申请号：US16953441

申请日：2020-11-20

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Sunil K. Singh ,  Johnatan A. Kantarovsky ,  Siva P. Adusumilli ,  Sebastian T. Ventrone ,  John J. Ellis-Monaghan ,  Yves T. Ngu

IPC: H01L23/544 ,  H01L23/00

Abstract: The disclosure provides a method to authenticate an integrated circuit (IC) structure. The method may include forming a first authentication film (AF) material within the IC structure. A composition of the first AF material is different from an adjacent material within the IC structure. The method includes converting the first AF material into a void within the IC structure. Additionally, the method includes creating an authentication map of the IC structure to include a location of the void in the IC structure for authentication of the IC structure.

公开(公告)号：US11322497B1

公开(公告)日：2022-05-03

申请号：US17172539

申请日：2021-02-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yves T. Ngu ,  Ephrem G. Gebreselasie ,  Vibhor Jain ,  Johnatan A. Kantarovsky

IPC: H01L27/102 ,  H01L23/525 ,  H01L23/62

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electronic fuse (e-fuse) cells integrated with a bipolar device and methods of manufacture. The structure includes: a bipolar device comprising a collector region, a base region and an emitter region; and an e-fuse integrated with and extending from the emitter region of the bipolar device.