公开(公告)号：DE69031768T2

公开(公告)日：1998-06-25

申请号：DE69031768

申请日：1990-05-16

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：ES2112250T3

公开(公告)日：1998-04-01

申请号：ES90305297

申请日：1990-05-16

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：CA2016399C

公开(公告)日：1996-04-09

申请号：CA2016399

申请日：1990-05-09

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08 ,  G06F13/00 ,  G06F12/00 ,  G06F13/16

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：CA2118995A1

公开(公告)日：1994-11-29

申请号：CA2118995

申请日：1994-03-14

Applicant: IBM

Inventor： AMINI NADER ,  BLAND PATRICK M ,  BOURY BECHARA F ,  HOFMANN RICHARD G ,  LOHMAN TERENCE J

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40

Abstract: An arbitration mechanism 42 is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24; (ii) a first system bus 36 which connects the CPU 24 to system memory 32 so that the CPU 24 can read data from, and write data to, the system memory 32; (iii) a second system bus 16 connected to the CPU 24; (iv) a host bridge 20 connecting the second-system bus 16 to a peripheral bus 22, the peripheral bus 22 having at least one peripheral device 18 attached thereto; and (v) an input/output (I/O) bridge 78 connecting the peripheral bus 22 to a standard I/O bus 92, the standard I/O bus 92 having a plurality of standard I/O devices 90 attached thereto. The arbitration mechanism 42 comprises (i) a first level 100 of logic for arbitrating between the plurality of standard I/O devices 90, wherein one standard I/O device 90 is selected from a plurality of the standard I/O devices 90 competing for access to the standard I/O bus 97, and (ii) a second level 102, 104 of logic for arbitrating between the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18, wherein one of the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18 is selected to access the peripheral bus 22. The arbitration mechanism 42 includes sideband signals which connect the first 100 and second levels 102, 104 of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device 90.

公开(公告)号：PL164259B1

公开(公告)日：1994-07-29

申请号：PL28568590

申请日：1990-06-19

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/362

Abstract: A logic circuit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

公开(公告)号：NZ233539A

公开(公告)日：1992-08-26

申请号：NZ23353990

申请日：1990-05-02

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：AU616604B2

公开(公告)日：1991-10-31

申请号：AU5506690

申请日：1990-05-15

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：IT8920625D0

公开(公告)日：1989-05-24

申请号：IT2062589

申请日：1989-05-24

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/08

Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

公开(公告)号：CA2299547C

公开(公告)日：2004-08-17

申请号：CA2299547

申请日：2000-02-25

Applicant: IBM

Inventor： BLAND PATRICK M ,  BEALKOWSKI RICHARD

IPC: G06F13/14 ,  G06F9/46 ,  G06F9/50 ,  G06F15/16 ,  G06F15/17

Abstract: A system for partitioning and allocating individual PCI slots within a Prima ry Host Bridge (PHB) in a partitioned computer system is provided. An innovative PHB system is included which allows a PCI slot to be dynamically assigned to one or more partitions at a given time, allowing for more efficient allocation of system resources.

公开(公告)号：CA2299550A1

公开(公告)日：2000-09-30

申请号：CA2299550

申请日：2000-02-25

Applicant: IBM

Inventor： BLAND PATRICK M ,  BEALKOWSKI RICHARD

IPC: G06F9/50 ,  G06F20060101 ,  G06F13/20 ,  G06F15/16 ,  G06F15/17 ,  G06F13/14

Abstract: A system and method for allowing multiple nodes of a multiprocessor system to share a set of I/O devices. A Cabinet Input/output Controller (CI/OC) is provided which manages communications between the multiprocessor system nodes and the common I/O devices, allowing individual nodes to access one or more of its target devices exclusively. Each of the nodes communicates with the CI/OC via a service processor, and the CI/OC interconnects the various I/O devices and a node's USB controller.