公开(公告)号：GB2349721A

公开(公告)日：2000-11-08

申请号：GB0000996

申请日：2000-01-18

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN

IPC: G06F12/08

Abstract: A non-uniform memory access (NUMA) data processing system includes first and second processing nodes 8a,8n that are each coupled to a node interconnect 22. The first processing node 8a includes a system memory 18 and first and second processors 10a,10m that each have a respective one of first and second cache hierarchies 14, which are coupled for communication by a local interconnect 16. The second processing node 8n includes at least a system memory and a third processor having a third cache hierarchy. The first cache hierarchy and the third cache hierarchy are permitted to concurrently store an unmodified copy of a particular cache line in a Recent coherency state from which the copy of the particular cache line can be sourced by shared intervention. In response to a request for the particular cache line by the second cache hierarchy, the first cache hierarchy sources a copy of the particular cache line to the second cache hierarchy by shared intervention utilizing communication on only the local interconnect 16 and without communication on the node interconnect 22.

公开(公告)号：BR9903228A

公开(公告)日：2000-10-03

申请号：BR9903228

申请日：1999-06-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  IACHETTA RICHARD NICHOLAS JR

IPC: G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one processor and a local system memory. The NUMA computer system further includes a transaction buffer, coupled to the interconnect, that stores communication transactions transmitted on the interconnect that are both initiated by and targeted at a processing node other than the third processing node. In response to a determination that a particular communication transaction originally targeting another processing node should be processed by the third processing node, buffer control logic coupled to the transaction buffer causes the particular communication transaction to be retrieved from the transaction buffer and processed by the third processing node. In one embodiment, the interconnect includes a broadcast fabric, and the transaction buffer and buffer control logic form a portion of the third processing node.

公开(公告)号：CA2279138A1

公开(公告)日：2000-02-17

申请号：CA2279138

申请日：1999-07-29

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  CARPENTER GARY DALE ,  IACHETTA RICHARD NICHOLAS JR

IPC: G06F15/16 ,  G06F12/08 ,  G06F12/02 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes a node interconnect and a plurality of processing nodes that each contain at least one processor, a local interconnect, a local system memory, and a node controller coupled to both a respective local interconnect and the node interconnect. According to the method of the present invention, a communication transaction is transmitted on the node interconnect from a local processing node to a remote processing node. In response to receipt of the communication transaction by the remote processing node, a response including a coherency response field is transmitted on the node interconnect from the remote processing node to the local processing node. In response to receipt of the response at the local processing node, a request is issued on the local interconnect of the local processing node concurrently with a determination of a coherency response indicated by the coherency response field.

公开(公告)号：DE69102850T2

公开(公告)日：1995-01-05

申请号：DE69102850

申请日：1991-09-06

Applicant: IBM

Inventor： CARPENTER GARY DALE

IPC: H03F1/02 ,  H03F1/32 ,  H03F1/52 ,  H03F3/30

Abstract: The provision of shoot-through protection with means for producing a low impedance path from the gate of each power transistor to its source conduction electrode (Vgs) if the Vgs at the other transistor is greater than a reference value. This additional circuitry permits the use of a desired driver circuit without modification, while preventing shoot-through whether from the driver signals or from high output dv/dt.

公开(公告)号：DE69738187D1

公开(公告)日：2007-11-22

申请号：DE69738187

申请日：1997-07-01

Applicant: IBM

Inventor： BULLER MARVIN LAWRENCE ,  CARPENTER GARY DALE ,  HOANG BINH THAI

IPC: H01L23/467 ,  H01L23/34 ,  H05K7/20

Abstract: Systems and methods for reducing the thermal stresses between an integrated circuit package and a printed circuit board, each having different thermal coefficients of expansion, to minimize thermal fatigue induced by power management cycling. The thermal impedance of the convection cooling system used with the integrated circuit package is switched with the state of the power management signal. A fan on the integrated circuit package heat sink is energized when the integrated circuit is operated in a high power mode and disabled when the integrated circuit is in a low power mode initiated by the power management system. The switching is directly responsive to the power management system and without regard to integrated circuit package temperature. The switching of the fan alters the thermal impedance to reduce the extremes of the temperature excursion and to materially reduce the rate of change of temperature experienced by the integrated circuit package. Relative temperature induced stresses on the connection between the printed circuit board and integrated circuit package are decreased.

公开(公告)号：CA2280125C

公开(公告)日：2003-01-07

申请号：CA2280125

申请日：1999-08-12

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  IACHETTA RICHARD NICHOLAS JR ,  CARPENTER GARY DALE ,  DEAN MARK EDWARD

IPC: G06F15/163 ,  G06F12/08 ,  G06F15/173

Abstract: The invention relates to memory access and provided non-uniform memory acces s (NUMA) data processing system includes a node interconnect to which at least a firs t processing node and a second processing node are coupled. The first and the second processing node s each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnec t and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the reques t transaction should be processed at the second processing node.

公开(公告)号：PL348253A1

公开(公告)日：2002-05-20

申请号：PL34825399

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F9/48 ,  G06F15/173 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：HU0104536A2

公开(公告)日：2002-03-28

申请号：HU0104536

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  DEBACKER PHILIPPE LOUIS ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F9/48 ,  G06F15/173 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：CZ20012154A3

公开(公告)日：2001-09-12

申请号：CZ20012154

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：DE69119346D1

公开(公告)日：1996-06-13

申请号：DE69119346

申请日：1991-08-29

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  LUNDBERG MARTIN BIRK

IPC: H03F3/30 ,  H03F3/345 ,  H03F3/50 ,  H03K17/16

Abstract: A power amplifier having a power MOS transistor output device. The gate drive for the power device is a bidirectional current source. In one form of the gate driver circuit, the bidirectional current source includes the capability of controlling the limits of the gate current, which in turn controls the slew rate of the power amplifier.