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    METHOD OF FORMING A MULTI-CHIP STACKED STRUCTURE INCLUDING A THIN INTERPOSER CHIP HAVING A FACE-TO-BACK BONDING WITH ANOTHER CHIP
    23.
    发明申请
    METHOD OF FORMING A MULTI-CHIP STACKED STRUCTURE INCLUDING A THIN INTERPOSER CHIP HAVING A FACE-TO-BACK BONDING WITH ANOTHER CHIP 审中-公开
    形成多芯片堆叠结构的方法，其中包括具有另一个芯片的面对背结合的薄间隙芯片

    公开(公告)号：WO2011119308A3

    公开(公告)日：2011-12-29

    申请号：PCT/US2011026957

    申请日：2011-03-03

    Applicant: IBM ,  FAROOQ MUKTA G ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

    Inventor： FAROOQ MUKTA G ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

    IPC: H01L23/48 ,  H01L23/12

    CPC classification number: H01L21/6835 ,  H01L23/3128 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/00

    Abstract: A temporary substrate (901) having an array of first solder pads (192) is bonded to the front side of a first substrate (101) by reflowing an array of first solder balls (250). The first substrate (101) is thinned by removing the back side, and an array of second solder pads (142) is formed on the back side surface of the first substrate (101). The assembly of the first substrate (101) and the temporary substrate (901) is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip (100) and a handle portion (900). A second semiconductor chip (200) is bonded to an assembly through an array of the second solder balls (150). The handle portion (900) is removed from each assembly by reflowing the array of the first solder balls (250), while the array of the second solder balls (150) does not refiow. The assembly is subsequently mounted on a packaging substrate (300) employing the array of the first solder balls (250).

    Abstract translation: 具有第一焊盘（192）的阵列的临时衬底（901）通过回流第一焊球（250）的阵列而接合到第一衬底（101）的前侧。 通过去除背面而使第一衬底（101）变薄，并且在第一衬底（101）的背侧表面上形成有第二焊盘（142）的阵列。 切割第一基板（101）和临时基板（901）的组装以形成多个堆叠，每个堆叠包括第一半导体芯片（100）和手柄部分（900）的组件。 第二半导体芯片（200）通过第二焊球（150）的阵列结合到组件。 通过回流第一焊球（250）的阵列，而第二焊球（150）的阵列不反射，从每个组件移除手柄部分（900）。 随后，使用第一焊球（250）的阵列将组件安装在包装衬底（300）上。

    OPTIMIZED ANNULAR COPPER TSV
    24.
    发明申请
    OPTIMIZED ANNULAR COPPER TSV 审中-公开
    优化的环形铜片TSV

    公开(公告)号：WO2012177585A3

    公开(公告)日：2013-04-25

    申请号：PCT/US2012043052

    申请日：2012-06-19

    Applicant: IBM ,  ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

    Inventor： ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

    IPC: H01L21/28 ,  H01L21/768

    CPC classification number: H01L21/76846 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

    Abstract translation: 本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。 衬底限定沟槽的内侧壁和外侧壁，该侧壁分隔5至10微米的距离。 包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。 基板厚度可以为60微米或更小。 具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。

    3-D INTEGRATION USING MULTI STAGE VIAS
    25.
    发明申请
    3-D INTEGRATION USING MULTI STAGE VIAS 审中-公开
    使用多级VIAS的三维集成

    公开(公告)号：WO2012151229A3

    公开(公告)日：2013-01-03

    申请号：PCT/US2012036038

    申请日：2012-05-02

    Applicant: IBM ,  FAROOQ MUKTA G ,  GRAVES-ABE TROY L

    Inventor： FAROOQ MUKTA G ,  GRAVES-ABE TROY L

    IPC: H01L21/768 ,  H01L21/28

    CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias.

    Abstract translation: 可以形成TSV，其具有通过顶部衬底表面形成的顶部截面，以及通过底部衬底表面形成的底部截面。 顶部截面可以具有对应于设计规则的最小横截面，并且顶部截面深度可对应于可工作的纵横比。 顶部通孔可以被填充或插入，以便可以继续顶部处理。 底部通孔可以具有更大的横截面，以便于形成穿过其中的导电路径。 底部部分通孔从顶部部分通孔的背面延伸到底部，并且在基板变薄之后形成。 可以通过在从接合的顶部和底部部分通孔去除牺牲填充材料之后形成导电路径来完成TSV。

    Leckstrom-Messstruktur und Verfahren für Leckstrommessung von Siliciumdurchkontaktierungen
    27.
    发明专利
    Leckstrom-Messstruktur und Verfahren für Leckstrommessung von Siliciumdurchkontaktierungen 未知

    公开(公告)号：DE112012003188B4

    公开(公告)日：2018-06-21

    申请号：DE112012003188

    申请日：2012-09-14

    Applicant: IBM

    Inventor： BHOOVARAGHAN BHAVANA ,  FAROOQ MUKTA G ,  KINSER EMILY ,  SAROOP SUDESH

    IPC: H01L21/66 ,  H01L21/768 ,  H01L23/52 ,  H01L23/544 ,  H01L27/12

    Abstract: Leckstrom-Messstruktur (200) für Durchkontaktierungen, die aufweist:ein Halbleitersubstrat (402), das eine aktive Schicht aufweist;eine Vielzahl von Substratdurchkontaktierungen (212A-E; 302; 412) in dem Halbleitersubstrat, die sich erheblich durch das Halbleitersubstrat erstrecken; undeine Leckstrom-Messstruktur, die sich in der aktiven Schicht des Halbleitersubstrats befindet, die aufweist:eine Vielzahl von Substratkontakten (214A-E; 306; 414), die sich in das Halbleitersubstrat erstrecken;eine Vielzahl von Erfassungsschaltungen, die mit der Vielzahl von Substratdurchkontaktierungen (216A-E; 300; 416) und mit der Vielzahl von Substratkontakten verbunden sind, wobei die Vielzahl von Erfassungsschaltungen eine Vielzahl von Ausgaben (310) bereitstellen, die auf einen Leckstrom aus der Vielzahl von Substratdurchkontaktierungen hindeuten;eine BIST-Maschine (222) für einen integrierten Selbsttest, um schrittweise eine Prüfung der Vielzahl von Substratdurchkontaktierungen durchzuführen; undeinen Speicher (218), der mit der BIST-Maschine verbunden ist, um die Ausgaben von der Vielzahl von Erfassungsschaltungen zu empfangen,wobei die Leckstrom-Messstruktur auf einen Leckstrom aus jeder der Substratdurchkontaktierungen in das Halbleitersubstrat und einen Leckstrom aus jeder der Substratdurchkontaktierungen in eine weitere Substratdurchkontaktierung prüft.

    Optimized annular copper TSV
    28.
    发明专利
    Optimized annular copper TSV 未知

    公开(公告)号：GB2505576B

    公开(公告)日：2016-03-23

    申请号：GB201318982

    申请日：2012-06-19

    Applicant: IBM

    Inventor： ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

    IPC: H01L23/48 ,  H01L21/28 ,  H01L21/768

    Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

    Semiconductor device having a copper plug
    29.
    发明专利
    Semiconductor device having a copper plug 未知

    公开(公告)号：GB2486357B

    公开(公告)日：2015-05-27

    申请号：GB201202913

    申请日：2010-08-23

    Applicant: IBM

    Inventor： FAROOQ MUKTA G ,  KINSER EMILY R ,  MELVILLE IAN D ,  SEMKOW KRYSTYNA W

    IPC: H01L23/532

    Abstract: Disclosed is a semiconductor device wherein an insulation layer has a via opening with an aluminum layer in the via opening and in contact with the last wiring layer of the device. There is a barrier layer on the aluminum layer followed by a copper plug which fills the via opening. Also disclosed is a process for making the semiconductor device.

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