公开(公告)号：US6360938B2

公开(公告)日：2002-03-26

申请号：US79459701

申请日：2001-02-27

Applicant: IBM

Inventor： DELAURENTIS STEPHEN A ,  INTERRANTE MARIO J ,  JACKSON RAYMOND A ,  KNICKERBOCKER JOHN U ,  RAY SUDIPTA K ,  STALTER KATHLEEN A

IPC: B23K1/018 ,  H01L21/687 ,  B23K31/02

CPC classification number: H01L21/687 ,  B23K1/018

Abstract: A process and apparatus for removing flip chips with C4 joints mounted on a multi-chip module by applying a tensile force to one or more removal member bonded to the back of one or more flip chips during heating of the module to a temperature sufficient to cause the C4 joints to become molten. The tensile force can either be a compressed spring, or a bi-metallic member which is flat at room temperature and becomes curved when heated to such temperature, or a memory alloy whose original shape is curved and which is bent flat at room temperature but returns to its original curved shape when heated to such temperature. An adhesive is used to bond the removal member to the chip to be removed and is a low temperature, fast curing adhesive with high temperature tolerance after curing.

Abstract translation: 一种用于通过在将模块加热到足以导致的温度的温度下向一个或多个倒装芯片的背面施加张力而将一个或多个去除构件施加拉力而移除通过安装在多芯片模块上的C4接头的倒装芯片的方法和装置 C4接头变得熔化。 张力可以是压缩弹簧，也可以是在室温下为平坦的双金属构件，在加热到这样的温度时变得弯曲，或者是原始形状弯曲并在室温下弯曲平坦但是返回的记忆合金 在加热到这样的温度时变成原来的弯曲形状。 使用粘合剂将去除构件粘合到要去除的芯片上，并且是固化后具有耐高温性的低温快速固化粘合剂。

公开(公告)号：EP1618605A4

公开(公告)日：2010-09-08

申请号：EP03790123

申请日：2003-11-25

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  INTERRANTE MARIO J

IPC: H01L23/48 ,  B23K35/26 ,  H01L23/485 ,  H01L23/498 ,  H01L23/52 ,  H01L29/40 ,  H05K3/34

CPC classification number: H01L24/10 ,  B23K35/262 ,  B23K2201/36 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10378 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/047 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00 ,  H01L2224/0401

公开(公告)号：JP2004188497A

公开(公告)日：2004-07-08

申请号：JP2003389972

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FAROOQ MUKTA G ,  INTERRANTE MARIO J ,  SABLINSKI WILLIAM E

IPC: B23K35/26 ,  C22C13/00 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H05K3/28 ,  H05K3/34

CPC classification number: H01L21/6835 ,  B23K35/262 ,  B23K2201/40 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81024 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3463 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a lead-free hierarchical structure for packaging electronic circuits.
SOLUTION: The electronic circuit package has the hierarchy of liquidus temperature in mutual joining of solder limiting fused degree of the mutually joining of the solder with a C4 (current controlled collapse chip joining) technique between the following second level joining /assembling-treatment and a rework-treatment. The solder hierarchy is used to Sn/Ag and Sn/Cu non-eutectic solder alloy having high liquidus temperature for mutually joining of the solder with the C4 technique at the first level and used to an alloy having low liquidus temperature for mutually joining the second level. When the joining/assembling treatment of a chip-carrier into a PCB is performed, the mutually joining part with the C4 technique is not fully fused. These continuously keep liquid having smaller amount than that of a fully fused alloy. This reduces the expansion of solder joining and as this result the stress is weakened in the mutually joining with the C4 technique.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002373923A

公开(公告)日：2002-12-26

申请号：JP2002131146

申请日：2002-05-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： JACKSON RAYMOND A ,  BRADLEY SCOTT A ,  DELAURENTIS STEPHEN A ,  INTERRANTE MARIO J ,  LINNELL DAVID C

IPC: H01L21/60 ,  B08B1/00 ,  B08B7/00 ,  B23K1/018 ,  H01L21/48 ,  H05K3/34

CPC classification number: B08B1/008 ,  B08B7/0071 ,  H01L21/4864 ,  H05K3/3436 ,  H05K3/3457

Abstract: PROBLEM TO BE SOLVED: To provide a method and an apparatus for removing BGA interconnections from a substrate and an interposer for rework.
SOLUTION: The method for removing at least one molten or solid structure from a surface is provided with the step of placing the surface with the at least one molten or solid structure in a fixture, the step of disposing a wiper block assembly made to act by bias at a region at least proximally to one molten or solid structure, the step of retaining the wiper block assembly in a first position with a device having a first temperature point level equivalent to or higher than a second melting point level of the at least one molten or solid structure, and the step of raising the temperature of the fixture to the first temperature point level. When the device reaches the first temperature point level, at least the one molten or solid structure is wiped off from the surface.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于从基板和插入件去除BGA互连以进行返工的方法和装置。 解决方案：从表面去除至少一个熔融或固体结构的方法具有将具有至少一个熔融或固体结构的表面放置在固定装置中的步骤，将设置为由 在至少近似于一个熔融或固体结构的区域处的偏压，将刮水块组件保持在第一位置的步骤，其中装置具有等于或高于所述至少一个的第二熔点水平的第一温度点水平 熔融或固体结构，以及将夹具的温度升高到第一温度点的步骤。 当装置达到第一温度点时，至少将一个熔融或固体结构从表面擦掉。

公开(公告)号：JP2002009433A

公开(公告)日：2002-01-11

申请号：JP2001130649

申请日：2001-04-27

Applicant: IBM

Inventor： INTERRANTE MARIO J ,  BRENDA PETERSON ,  SDIPTA K RAY ,  WILLIAM E SABURINSKI ,  AMITT K SHAAKUHERU

IPC: B23K35/26 ,  C22C9/02 ,  C22C9/05 ,  C22C13/00 ,  C22C13/02 ,  H01L23/12 ,  H01L23/488 ,  H01L23/498 ,  H05K3/34 ,  H05K3/40

Abstract: PROBLEM TO BE SOLVED: To provide a new semiconductor chip carrier connection which has a chip carrier and a 2nd level assembly formed by a surface amount technology. SOLUTION: The surface mount technology for a ball grid array(BGA), a column grid array(CGA), etc., is adopted and basically includes a non-solder metal connection such as a copper connection. This invention is concerned with a column grid array structure and its process.

公开(公告)号：JP2000340712A

公开(公告)日：2000-12-08

申请号：JP2000109574

申请日：2000-04-11

Applicant: IBM

Inventor： INTERRANTE MARIO J ,  RAYMOND ALAN JACKSON ,  SUDEIPUTA KUMAA RAY ,  PAUL A ZUKKO ,  SCOTT R DWYER

IPC: H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To mechanically stabilize column grid wires on a substrate by coating column grid array wires with a polymer of low glass-transition temperature on a substrate, after their mounting. SOLUTION: A standard ceramic wire column grid array, which is to be mounted on a substrate is used to which a thin polymer coating 50 is added, in such a way as to cover fillets of a wire column 32. The polymer 50, having proper coating and temperature characteristics, is applicable to distributed or spin coating in order to obtain a thin conformed coating on fillets of the wire column 32. The substrate 30 is generally made of ceramic, but an organic substrate or a silicon substrate may be used, if satisfactory adhesion of the polymer can be made. The glass transition temperature of the polymer 50, at which the polymer softens, is lower than the melting point of a lead/tin alloy used to form the wire column 32. The polymer 50 adheres to the ceramic substrate 30 and to the lower side of a metal pad 34, and causes the wire column 32 to adhere to the surface of the lead/tin alloy solder.

公开(公告)号：DE102012103571A1

公开(公告)日：2012-11-22

申请号：DE102012103571

申请日：2012-04-24

Applicant: IBM

Inventor： SHAPIRO MICHAEL JAY ,  WASSICK THOMAS ANTHONY ,  INTERRANTE MARIO J ,  LAFONTANT GARY ,  WEBB BUCKNELL C

IPC: H01L21/283 ,  H01L23/50 ,  H01L21/768

Abstract: Es wird eine Halbleiterstruktur beschrieben, die eine Vielzahl übereinander gestapelter Halbleiterchips in einer dreidimensionalen Anordnung beinhaltet. Ein erster Halbleiterchip steht in Kontakt mit einem zweiten Halbleiterchip. Der erste Halbleiterchip beinhaltet eine Silicium-Durchkontaktierung (TSV), welche sich durch den ersten Halbleiterchip hindurch erstreckt; eine elektrisch leitende Kontaktfläche an einer Oberfläche des ersten Halbleiterchips, wobei die TSV in Kontakt mit einer ersten Seite der elektrisch leitenden Kontaktfläche endet; eine Passivierungsschicht, welche die elektrisch leitende Kontaktfläche bedeckt, wobei die Passivierungsschicht eine Vielzahl von Öffnungen aufweist; und eine Vielzahl elektrisch leitender Strukturen, welche in der Vielzahl von Öffnungen und in Kontakt mit einer zweiten Seite der elektrisch leitenden Kontaktfläche ausgebildet sind, wobei der Kontakt der Vielzahl elektrisch leitender Strukturen mit der elektrisch leitenden Kontaktfläche in Bezug auf den Kontakt der TSV mit der elektrisch leitenden Kontaktfläche versetzt ist.

公开(公告)号：AU2003293133A1

公开(公告)日：2004-11-23

申请号：AU2003293133

申请日：2003-11-25

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  INTERRANTE MARIO J

IPC: H01L23/485 ,  H01L23/498 ,  H05K3/34 ,  H01L23/48 ,  H01L29/40 ,  H01L23/52

Abstract: A lead free solder hierarchy structure for electronic packaging that includes organic interposers. The assembly may also contain passive components as well as underfill material. The lead free solder hierarchy also provides a lead free solder solution for the attachment of a heat sink to the circuit chip with a suitable lead free solder alloy.

公开(公告)号：DE102012103571B4

公开(公告)日：2013-12-05

申请号：DE102012103571

申请日：2012-04-24

Applicant: IBM

Inventor： SHAPIRO MICHAEL JAY ,  WASSICK THOMAS ANTHONY ,  INTERRANTE MARIO J ,  LAFONTANT GARY ,  WEBB BUCKNELL C

IPC: H01L23/50 ,  H01L21/283 ,  H01L21/60 ,  H01L21/768

Abstract: Halbleiterstruktur, umfassend: eine Silicium-Durchkontaktierung (TSV), welche sich durch die Halbleiterstruktur erstreckt; eine elektrisch leitende Kontaktfläche an einer Oberfläche der Halbleiterstruktur, wobei die TSV in Kontakt mit einer ersten Seite der elektrisch leitenden Kontaktfläche endet; eine Passivierungsschicht, welche die elektrisch leitende Kontaktfläche bedeckt, wobei die Passivierungsschicht eine Vielzahl von Öffnungen aufweist; und eine Vielzahl elektrisch leitender Strukturen, welche in der Vielzahl von Öffnungen und in Kontakt mit einer zweiten Seite der elektrisch leitenden Kontaktfläche ausgebildet sind, wobei der Kontakt der Vielzahl elektrisch leitender Strukturen mit der elektrisch leitenden Kontaktfläche in Bezug auf den Kontakt der TSV mit der elektrisch leitenden Kantaktfläche versetzt ist.

公开(公告)号：MY126247A

公开(公告)日：2006-09-29

申请号：MYPI20022733

申请日：2002-07-18

Applicant: IBM

Inventor： ALCOE DAVID JANES ,  STUTZMAN RANDALL JOSEPH ,  WEISMAN RENEE L ,  ZITZ JEFFREY ALLEN ,  COFFIN JEFFREY THOMAS ,  GAYNES MICHAEL ANTHONY ,  HAMEL HARVEY CHARLES ,  INTERRANTE MARIO J ,  PETERSON BRENDA LEE ,  SHANNON MEGAN J ,  SABLINSKI WILLIAM EDWARD ,  SPRING CHRISTOPHER TODD

IPC: H01L23/29 ,  H01L23/552 ,  H01L23/31 ,  H05K9/00

Abstract: ELECTRONIC PACKAGES INCORPORATING EMI SHIELDING, AND PARTICULARLY SEMICONDUCTOR DEVICES WHICH INCORPORATED SEMICONDUCTOR CHIP-CARRIER STRUCTURES HAVING GROUNDED BANDS EMBEDDED THEREIN WHICH ARE ADAPTED TO REDUCE OUTGOING AND INCLUDENT EMI EMISSIONS FOR HIGH-SPEED SWITCHING ELECTRONIC PACKAGES. (FIG. 1)