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    Managing processing associated with selected architectural facilities
    24.
    发明专利
    Managing processing associated with selected architectural facilities 未知

    公开(公告)号：AU2015233738B2

    公开(公告)日：2018-03-01

    申请号：AU2015233738

    申请日：2015-03-09

    Applicant: IBM

    Inventor： GSCHWIND MICHAEL KARL ,  GAINEY CHARLES

    IPC: G06F9/455 ,  G06F9/30

    Abstract: A facility is provided that, when installed, removes from an architecture a selected architectural function, such that the function is not able to be turned on/off regardless of other controls within the environment. When the facility is installed, the architectural function is not supported when processing in an architectural mode based on the architecture. It is as if the selected architectural function is no longer available in the architecture, and in fact, the code implementing the facility may have been deleted, bypassed, or otherwise eliminated. One such architectural function is virtual address translation, such as dynamic address translation (DAT), and the architecture is, for instance, ESA/390.

    Uso de una funcionalidad de interrupción con margen de advertencia por un programa
    25.
    发明专利
    Uso de una funcionalidad de interrupción con margen de advertencia por un programa 未知

    公开(公告)号：ES2598816T3

    公开(公告)日：2017-01-30

    申请号：ES12866318

    申请日：2012-11-13

    Applicant: IBM

    Inventor： GAINEY CHARLES ,  KUBALA JEFFREY ,  FARRELL MARK ,  SCHMIDT DONALD ,  MULDER JAMES ,  PIERCE BERNARD ,  ROGERS ROBERT

    IPC: G06F9/46 ,  G06F9/54 ,  G06F11/14

    Abstract: Un sistema informático (200) para facilitar el procesamiento en un entorno informático, comprendiendo dicho sistema informático: una memoria; y un procesador en comunicación con la memoria, en donde el sistema informático está configurado para realizar un método, comprendiendo dicho método: que un programa obtenga una indicación de una funcionalidad de margen de advertencia instalada (700) dentro del entorno informático, donde la funcionalidad de margen de advertencia proporciona al programa un período de gracia de margen de advertencia para realizar una función; que el programa inicie, basándose en la obtención de la indicación de que la funcionalidad de margen de advertencia está instalada, la inscripción del programa en el registro de la funcionalidad de margen de advertencia (702), comprendiendo la inscripción en el registro una petición no solicitada de inscripción en el registro que indica que el programa entiende un protocolo de la funcionalidad de margen de advertencia y pretende participar en la funcionalidad de margen de advertencia; que el programa reciba una notificación de margen de advertencia que indica que ha comenzado el período de gracia de margen de advertencia, siendo la inscripción del programa en el registro de la funcionalidad de margen de advertencia un requisito previo para recibir la notificación de margen de advertencia, en donde si el programa no está registrado, entonces no se ofrece período de gracia; y que el programa, basándose en la notificación de margen de advertencia, al menos inicie la función dentro del período de gracia de margen de advertencia.

    Architectural mode configuration in a computing system
    26.
    发明专利
    Architectural mode configuration in a computing system 未知

    公开(公告)号：AU2015230885A1

    公开(公告)日：2016-08-04

    申请号：AU2015230885

    申请日：2015-03-09

    Applicant: IBM

    Inventor： GSCHWIND MICHAEL KARL ,  GAINEY CHARLES

    IPC: G06F9/44 ,  G06F9/30

    Abstract: A determination is made that a configuration architectural mode facility is installed in a computing environment that is configured for a plurality of architectural modes and has a defined power-on sequence that is to power-on the computing environment in one architectural mode of the plurality of architectural modes. Based on determining that the configuration architectural mode facility is installed, the computing environment is reconfigured to restrict use of the one architectural mode. The reconfiguring includes selecting a different power-on sequence to power-on the computing environment in another architectural mode of the plurality of architectural modes, wherein the another architectural mode is different from the one architectural mode, and executing the different power-on sequence to power-on the computing environment in the another architectural mode in place of the one architectural mode restricting use of the one architectural mode.

    DYNAMIC ENABLEMENT OF MULTITHREADING
    30.
    发明专利
    DYNAMIC ENABLEMENT OF MULTITHREADING 未知

    公开(公告)号：CA2940905C

    公开(公告)日：2022-08-16

    申请号：CA2940905

    申请日：2015-03-19

    Applicant: IBM

    Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY CHARLES ,  JACOBI CHRISTIAN

    IPC: G06F9/46 ,  G06F9/50

    Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

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