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    22.
    发明专利
    未知

    公开(公告)号：AT131640T

    公开(公告)日：1995-12-15

    申请号：AT90306343

    申请日：1990-06-11

    Applicant: IBM

    Inventor： DIXON JERRY DUANE ,  KEENER DON STEVEN ,  LOCKER HOWARD JEFFREY ,  MARAZAS GERALD ALLAN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN

    IPC: G06F13/14 ,  G06F12/06

    Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

    23.
    发明专利
    未知

    公开(公告)号：DE3687012T2

    公开(公告)日：1993-04-15

    申请号：DE3687012

    申请日：1986-04-18

    Applicant: IBM

    Inventor： KEENER DON STEVEN

    IPC: G11B21/08 ,  G11B5/55 ,  G11B5/596 ,  G11B21/10 ,  G11B21/00

    Abstract: Technique for dynamically maintaining alignment of servo controls (12) in a disk (D1, D2) drive system which uses external indicia (Q, R) to position the head assembly (8) between tracks containing embedded servo signals; the latter used to control track following. Plural pairs of phase staggered track reference signals are derived from the external indicia (Q, R) , and during system initialization an optimal pair is selected for controlling head (8) positioning. The system is initialized both at power up time and after detection of certain errors. The selection is made by using each pair separately to direct positioning of the head assembly (8) over a predetermined range of sampling positions at each of which centering offsets relative to the embedded servo signals are measured and recorded in association with the respective pair. Based on an evaluation of these offsets, the system microprocessor (16) selects a reference signal pair having the least average offset to control subsequent head (8) positioning operations. The system is then readied for "normal" read/write operation.

    PHYSICAL PARTITIONING OF LOGICALLY CONTINUOUS BUS
    24.
    发明专利
    PHYSICAL PARTITIONING OF LOGICALLY CONTINUOUS BUS 未知

    公开(公告)号：CA2092631C

    公开(公告)日：1997-04-08

    申请号：CA2092631

    申请日：1993-03-12

    Applicant: IBM

    Inventor： KEENER DON STEVEN ,  MCNEILL ANDREW BOYCE ,  SCHEIERN KEVIN LEE ,  NEWSOM THOMAS HAROLD ,  VOORHEES RICHARD W ,  WACHTEL EDWARD IRVING

    IPC: G06F13/36 ,  G06F13/40 ,  G06F13/16

    Abstract: Arrangements are disclosed for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

    27.
    发明专利
    未知

    公开(公告)号：DE68923433T2

    公开(公告)日：1996-03-07

    申请号：DE68923433

    申请日：1989-11-30

    Applicant: IBM

    Inventor： BUSH GREGORY FREDERICK ,  KEENER DON STEVEN ,  MOREL JEANNE ELLEN ,  VOORHEES RICHARD W

    IPC: G06F12/06

    Abstract: In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its output to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).

    28.
    发明专利
    未知

    公开(公告)号：DE68923433D1

    公开(公告)日：1995-08-17

    申请号：DE68923433

    申请日：1989-11-30

    Applicant: IBM

    Inventor： BUSH GREGORY FREDERICK ,  KEENER DON STEVEN ,  MOREL JEANNE ELLEN ,  VOORHEES RICHARD W

    IPC: G06F12/06

    Abstract: In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its output to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).

    INCREASING OPTIONS IN LOCATING ROM IN MEMORY SPACE
    29.
    发明专利
    INCREASING OPTIONS IN LOCATING ROM IN MEMORY SPACE 未知

    公开(公告)号：NZ231639A

    公开(公告)日：1992-03-26

    申请号：NZ23163989

    申请日：1989-12-05

    Applicant: IBM

    Inventor： BUSH GREGORY FREDERICK ,  KEENER DON STEVEN ,  MOREL JEANNE ELLEN ,  VOORHEES RICHARD W

    IPC: G06F12/06 ,  G06F9/24

    Abstract: In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its output to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).

    30.
    发明专利
    未知

    公开(公告)号：BR8906348A

    公开(公告)日：1990-08-21

    申请号：BR8906348

    申请日：1989-12-08

    Applicant: IBM

    Inventor： BUSH GREGORY FREDERICK ,  KEENER DON STEVEN ,  MOREL JEANNE ELLEN ,  VOORHEES RICHARD W

    IPC: G06F12/06 ,  G06F12/02

    Abstract: In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its output to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).

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