公开(公告)号：WO2005089086A2

公开(公告)日：2005-09-29

申请号：PCT/US2004027650

申请日：2004-08-25

Applicant: IBM ,  KIRIHATA TOSHIAKI

Inventor： KIRIHATA TOSHIAKI

IPC: G11C7/12 ,  G11C7/14 ,  G11C11/4094 ,  G11C11/4099

CPC classification number: G11C11/405 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4094 ,  G11C11/4099

Abstract: A dynamic random access memory (DRAM) storage device includes a storage cell having a plurality of transistors arranged in a gain cell configuration, the gain cell coupled to a read bitline and a write bitline. A dummy cell is configured as a clamping device for the read bitline, wherein the dummy cell opposes a read bitline voltage swing during a read operation of the storage cell.

Abstract translation: 动态随机存取存储器（DRAM）存储器件包括具有以增益单元配置排列的多个晶体管的存储单元，所述增益单元耦合到读位线和写位线。 虚拟单元被配置为用于读取位线的钳位装置，其中该虚拟单元在存储单元的读取操作期间与读取的位线电压摆动相对。

公开(公告)号：WO0193273A3

公开(公告)日：2002-08-08

申请号：PCT/US0117441

申请日：2001-05-31

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  NETIS DMITRY

IPC: G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/10

CPC classification number: G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4097

Abstract: There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups (102); at least one sense amplifier (SA); a first and a second multiplexer (MUXs); and at least one programmable control device (control circuit). Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.

Abstract translation: 提供了一种半导体存储器件，其包括：布置在至少两组（102）中的多个存储单元; 至少一个读出放大器（SA）; 第一和第二多路复用器（MUX）; 和至少一个可编程控制装置（控制电路）。 每个多路复用器适于将至少一个组耦合到放大器。 可编程控制装置适于控制第一和第二多路复用器。 在一个实施例中，可编程控制装置适于独立地控制多路复用器。

公开(公告)号：WO0143135A9

公开(公告)日：2002-05-16

申请号：PCT/US0032921

申请日：2000-12-05

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID R ,  KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  H03K17/22 ,  H03K19/0175

CPC classification number: G11C7/1072 ,  G11C7/1078

Abstract: A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.

Abstract translation: 用于随机存取存储器（RAM）的预取输入写入驱动器和包括预取输入写入驱动器的RAM。 预取输入写入驱动器特别适用于同步动态RAM（SDRAM）。 预取输入写入驱动器包括数据输入级接收数据，使能级接收对应的数据使能，以及写入驱动器，响应于写入信号和相应的使能级状态向存储器阵列提供接收到的数据。 数据级和使能级可以各自包括两个或更多个串联连接的三状态驱动器和每个三状态驱动器的输出端的锁存器。 当数据通过数据阶段时，相应的使能状态通过使能阶段。 如果使能状态指示要将数据级中的数据写入阵列，则将数据传递到RAM阵列。

公开(公告)号：JP2005203092A

公开(公告)日：2005-07-28

申请号：JP2005007728

申请日：2005-01-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BARTH JR JOHN E ,  KIRIHATA TOSHIAKI ,  PAUL C PARIIZU

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/406 ,  G11C2207/104

Abstract: PROBLEM TO BE SOLVED: To provide a concurrent refresh mode using distributed row address counter in a buried dynamic random access memory.
SOLUTION: A concurrent refresh mode is realized by refreshing the memory array by refresh bank selection signals while enabling concurrent memory access in another array. The refresh address management is simplified sharply by inserting a row address counter incorporated in each array. In a desirable embodiment of this invention, an arbitrary combination of two or more memory arrays is refreshed concurrently while enabling memory access. This concurrent mode also supports a multibank operation.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：在掩埋式动态随机存取存储器中提供使用分布式行地址计数器的并发刷新模式。 解决方案：通过刷新存储体选择信号刷新存储器阵列，同时实现另一阵列中的并发存储器访问，实现并发刷新模式。 通过插入并入每个阵列中的行地址计数器，刷新地址管理被简化。 在本发明的理想实施例中，同时刷新两个或更多个存储器阵列的任意组合，同时允许存储器访问。 此并发模式还支持多银行操作。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003030987A

公开(公告)日：2003-01-31

申请号：JP2002142731

申请日：2002-05-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： FIFIELD JOHN A ,  STORASKA DANIEL W ,  WIN K RUK ,  STEPHENS JEREMY K ,  KIRIHATA TOSHIAKI

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/4091

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C11/4091

Abstract: PROBLEM TO BE SOLVED: To provide a memory architecture, in which coupling noise between bit lines is small at CMOS intersection coupling sensing operation, and which operates at a high speed.
SOLUTION: In a single bit-line direct sensing architecture, a sense amplifier circuit, having four transistors arranged for each memory array, is used. In this circuit, the transistor functions so that a data bit from a true bit-line of a pair of bit line or an auxiliary bit line is transferred selective to a data line. The data line is preferably arranged on a plurality of memory arrays, and the data line may not be required, to share in read operation and write operation. Furthermore, digital sensing scheme function is performed, by charging a data line during read-out operation using one more current source detecting the ratio of a current source, driving by a bit line of a corresponding array and resistance of a transistor.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种存储架构，其中位线之间的耦合噪声在CMOS交叉耦合感测操作处较小，并且以高速运行。 解决方案：在单个位线直接感测架构中，使用具有为每个存储器阵列布置的四个晶体管的读出放大器电路。 在该电路中，晶体管起作用，使得来自一对位线或辅助位线的真位置的数据位被选择性地传送到数据线。 数据线优选地布置在多个存储器阵列上，并且可能不需要数据线，以共享读操作和写操作。 此外，通过使用检测电流源的比例的一个电流源，通过相应阵列的位线驱动和晶体管的电阻来驱动读出操作期间的数据线，执行数字感测方案功能。

公开(公告)号：JP2001273790A

公开(公告)日：2001-10-05

申请号：JP2001048272

申请日：2001-02-23

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： KIRIHATA TOSHIAKI ,  GABRIEL DANIEL

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To provide a memory device including a means coupling plural data storing cells, at least one redundant data storing cell, a redundant match detecting circuit, and a programmable fuse to a redundant match detecting circuit. SOLUTION: When a redundant match detecting circuit detects the prescribed condition set by a programmable fuse, a defective data is replaced by one redundant data storage region. Decoding is achieved by selecting an (e) fuse to be cut off by a data bus. Data bus, also, reads a state of the (e) fuse, and is used for guaranteeing that the (e) fuse is correctly cut off. Electric power is applied effectively to a selected (e) fuse while the data bus is shared to decode and verify the (e) fuse. Time-muliplex is used for transfer operation to reduce the number of communication channels between the (e) fuse and the redundant match detecting circuit, and transferring successively (e) fuse information to the redundant match detecting circuit can be performed. Actual time-multiplex operation for performing transfer is preferable to make 'enable' only after a chip is made a power source apply state.

公开(公告)号：JP2001176269A

公开(公告)日：2001-06-29

申请号：JP2000315712

申请日：2000-10-16

Applicant: IBM

Inventor： KORTS PAUL W ,  HORVEYS WILLIAM PAUL ,  BRIAN LI JI ,  KIRIHATA TOSHIAKI ,  JOHN MICHAEL ROSS ,  WILLIAM U SHEN

IPC: G06F12/16 ,  G06F12/02 ,  G11C8/08 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To provide a selectable function which makes the address portion of data words separable and enables the address portion to be used for a different purpose without disturbing the contents stored in a memory array. SOLUTION: A memory assembly which has an input port 242, an output port 216, and the memory array 23 containing a plurality of addressable storing positions in one mode contains the selectable function which sends the address information portion 212 of data which appear in a data route to other processing routes 770 and 771 by by-passing the memory array 232 without disturbing the information stored at the addressable storing positions.

公开(公告)号：JP2000353750A

公开(公告)日：2000-12-19

申请号：JP2000144824

申请日：2000-05-17

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRINTZINGER AXEL ,  KIRIHATA TOSHIAKI ,  NARAYAN CHANDRASEKHAR

IPC: H01L21/82 ,  H01H85/00 ,  H01L23/525 ,  H01H85/044

Abstract: PROBLEM TO BE SOLVED: To array a larger number of fuses densely by electrically connecting at least two fuses that contain a fusing part arrayed in a first level of a multi- layer semiconductor device, respectively. SOLUTION: Each fuse 13 contains a part 15 that is actually fused. The part 15 to be fused is arrayed in a first metal level M1. Like the other part of the fuse 13, the part 15 that is actually fused is made typically of a electrically conductive material, especially aluminum. A termination of each part 15 to be fused is connected to a connector bias 17 that connects that fuse 13 with a connector 19. A gate contact 23 is vertical to a direction of the fuse 13. The gate contact 23 can be connected to a ground that is common to all of existing fuse circuits. Therefore, fuse density is doubled without narrowing the fuse pitch.

公开(公告)号：JP2000251468A

公开(公告)日：2000-09-14

申请号：JP2000034052

申请日：2000-02-10

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To increase data speed or band width by arranging a pre-fetch circuit so that data speed among each hierarchy stage is all equalized substantially and controlling a latch so that the respective data speed at each hierarchy stage is all maintained. SOLUTION: Stages A-C have different data speed/signal time (data speed/bit) a, b, c respectively. Data speed at each stage is determined by data speed/signal path (selected by the number of signal path that is the number of pre-fetch). Pre-fetch is constituted between stages A-B of m>=int(a/b), pre-fetch is constituted between stages B-C of n>=int(b/c), and integers m, n are adjusted as desired. In order to vary pre-fetch depth at each stage, a pointer is designed so as to correspond to pre-fetch depth. A pointer signal is supplied by using a control circuit 214, the control circuit 214 latches continuously data made to synchronize with the latch included in a pre-fetch circuit, and timing is performed optimally.

公开(公告)号：JP2000235786A

公开(公告)日：2000-08-29

申请号：JP2000035922

申请日：2000-02-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  GERD FRANKOVSKI

IPC: G11C7/00 ,  G11C7/10 ,  G11C19/00 ,  G11C19/28 ,  H03K17/22 ,  H03K19/096

Abstract: PROBLEM TO BE SOLVED: To obtain a low voltage bus signalling architecture by providing a storage circuit which stores data after it is placed in a set state, an output circuit which connects stored data to an output by responding to an output strobe pulse and a reset circuit resetting the storage circuit by responding to the falling edge of the output strobe pulse. SOLUTION: This low voltage bus signalling architecture 20 has a driver 200 and a storage part 210. The driver 200 is an n-channel MOSFET inverter and inputs an input logic signal being on a line 203. The storage part 210 has a latch 250, an output circuit 260 and a reset circuit 270. The output circuit 260 connects stored data to an output DQ by responding to an output strobe pulse PNTo1. The reset circuit 270 precharges the storage part 210 via a first transistor 240 by responding to the falling edge of the pulse PNTo1.