公开(公告)号：CA1049154A

公开(公告)日：1979-02-20

申请号：CA261431

申请日：1976-09-17

Applicant: IBM

Inventor： JOY RICHARD C ,  MAGDO INGRID E ,  PHILLIPS ALFRED JR

IPC: H01L21/331 ,  H01L29/73 ,  H01L29/78

Abstract: FIELD EFFECT TRANSISTOR HAVING IMPROVED THRESHOLD STABILITY An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer. In the method for forming the field effect transistor, an impurity is introduced into the semi.conductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact. In an alternate embodiment of the method for forming a field effect transistor, a first ion implantation is formed in the drain region, such that the peak impurity concentration is located well within the body spaced from the surface thereof, and a second ion implantation, or diffusion, performed forming the source and also the ohmic contact for the drain which is located over the first region and within the first implanted region.

公开(公告)号：CA1019462A

公开(公告)日：1977-10-18

申请号：CA213805

申请日：1974-11-15

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/80 ,  H01L21/331 ,  H01L21/337 ,  H01L21/762 ,  H01L27/00 ,  H01L29/00 ,  H01L29/73 ,  H01L29/808

Abstract: A space charge limited transistor formed on a high resistivity substrate of at least 10,000 ohm-centimeter silicon of one conductivity type. One surface of the substrate is provided with spaced recessed oxide regions. The alternate spaces between the oxide regions are occupied by impurity zones of said one conductivity type. The intervening alternate spaces between the oxide regions are occupied by impurity zones of the other conductivity type. The impurity concentrations of the aforesaid impurity zones are at least several orders of magnitude higher than that of the substrate where the zones are separated from each other by the aforesaid oxide regions. The dielectric relaxation time is much larger than the carrier transit time within the substrate below and between adjacent impurity zones of the same conductivity type.

公开(公告)号：FR2340621A1

公开(公告)日：1977-09-02

申请号：FR7623637

申请日：1976-07-27

Applicant: IBM

Inventor： JOY RICHARD C ,  MAGDO INGRID E ,  PHILLIPS ALFRED JR

IPC: H01L21/331 ,  H01L29/73 ,  H01L29/78 ,  H01L29/76

公开(公告)号：CA992219A

公开(公告)日：1976-06-29

申请号：CA171590

申请日：1973-05-15

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/73 ,  H01L21/22 ,  H01L21/32 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/082 ,  H01L29/78

Abstract: A method of fabricating a planar dielectrically isolated semiconductor device by depositing a surface layer of dielectric material on a major surface of a monocrystalline substrate, removing portions of the layer to define annular channels, thermally oxidizing the exposed surface areas thereby forming annular ridges of SiO2, removing portions of the dielectric layer, selectively growing an epitaxial silicon layer over the surface wherein the surfaces of the annular ridges of SiO2 and the regions of epitaxial silicon are substantially co-planar.

公开(公告)号：CA976666A

公开(公告)日：1975-10-21

申请号：CA144164

申请日：1972-06-08

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L21/20 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L23/535 ,  H01L27/00

Abstract: 1360130 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 24 May 1972 [18 June 1971] 24380/72 Heading H1K A method of making a semi-conductor device comprises forming a dielectric layer on a monocrystalline substrate, opening a window in the layer, growing an epitaxial layer in the window and continuing the growth over the dielectric layer surrounding the window thus forming monocrystalline material within and above the window and polycrystalline material above the dielectric, forming a component in the monocrystalline material and applying a contact for the component to the polycrystalline material, the lateral extent of the polycrystalline material being bounded by a second dielectric layer formed on the first layer. In a first embodiment, Figs. 1 to 4, a bi-polar transistor is produced by diffusing P, As or Sb through a mask to form an N + -type subcollector region 24 in a P--type substrate 20, removing the mask and oxidizing to form a thin protective layer on which a first thick SiO 2 layer 23 is applied by sputtering. A thin layer 25 of Si 3 N 4 is deposited and covered with a second thick SiO 2 layer 26. Apertures 28, 30, 32 are selectively etched through the insulating layers and P-type Si is epitaxially deposited in the apertures to the thickness of the first SiO 2 layer 23. These deposits are monocrystalline and in the apertures 30, 32 above the subcollector region the P-type material is converted to N-type due to redistribution of impurities. The part of the top SiO 2 layer surrounding the aperture 32 is removed by selective etching to define the device area 34, the Si 3 N 4 layer 25 preventing removal of the lower SiO 2 layer. P-type Si is then epitaxially deposited to fill the apertures. The material in the device region 34 is monocrystalline above the aperture 32 and is surrounded with polycrystalline material over the exposed Si 3 N 4 layer. The material deposited in the upper part of the aperture 30 is converted to N-type by diffusion to form a collector reach-through and an N + -type emitter region 36 is diffused into the monocrystalline part of the device region which forms the base of the transistor. A layer of metal is deposited and patterned to form contacts, the base connection being made via the polycrystalline material. The device may be modified to produce an inverse transistor so that region 36 forms the collector. In a second embodiment, Figs. 5 to 8 (not shown), a P--type Si wafer (20) with an N + -type sub-collector region (24) is provided with an insulating layer (26) by sputtering a thick layer SiO 2 and covering with a thin layer of Si 3 N 4 . Two apertures (40, 42) are formed above the sub-collector region and one aperture (44) which defines a resistor region is formed above the substrate. Si is epitaxially deposited in the openings and over the top of the insulating layer, the material being undoped or N--type until the apertures are filled and the dopant then being changed to P-type. The deposited material is monocrystalline within and above the apertures (40, 42, 44) but polycrystalline above the insulating layer. The surface is oxidized and unwanted portions of the epitaxial layer are etched away to leave the monocrystalline region surrounded by polycrystalline material over one of the apertures to form the device region and to leave the monocrystalline deposits within the other apertures. The surface is re-oxidized and P or As is selectively diffused into the reach-through and resistor areas, and As, P or Sb is selectively diffused-in to form the N + -type emitter region in the monocrystalline part of the base region and to heavily dope the collector and resistor contact regions. Al electrodes are then applied. In a modification, Fig. 9 (not shown), instead of removing parts of the deposited P-type layer, isolation is achieved by selective thermal oxidation of the polycrystalline Si. In another embodiment, Figs. 10 to 12 (not shown) an N + -type sub-collector region (24) is formed in a P-type substrate (20), the surface is oxidized (62) and covered with Si 3 N 4 (64) and two windows (66, 68) are opened above the sub-collector region. A thick layer (70) of SiO 2 is pyrolytically deposited and windows (72, 74) are opened aligned with those in the underlayers but one being of larger area. An undoped layer (76) is epitaxially grown in the windows, the deposit in the smaller windows being monocrystalline and that in the other window having a monocrystalline cone surrounded by polycrystalline material. P or As is selectively diffused onto the collector reach-through region (80), a P-type impurity is diffused onto the monocrystalline and polycrystalline base region and finally P or As is selectively diffused to form the emitter region (81) in the monocrystalline part of the base region and to form the collector contact region. Contacts are applied as before. In a further embodiment, Figs. 13 to 15 (not shown), an MOS transistor is produced by thermally oxidizing the surface of a P--type layer (82), depositing a layer (86) of Si 3 N 4 , opening a window (88) in the Si 3 N 4 layer, depositing a thick layer (90) of SiO 2 pyrolytically or by sputtering, and opening a larger window (92) in the thick SiO 2 layer. P-type material is epitaxially deposited to fill the windows and forms a monocrystalline core (94) flanked by polycrystalline material. The surface is oxidized and P or As is selectively diffused into the polycrystalline material to form the source and drain regions (98, 100), the edges of the monocrystalline region also being doped to form the active parts of these regions. The device is then completed by conventional processing.

公开(公告)号：DE2458735A1

公开(公告)日：1975-07-10

申请号：DE2458735

申请日：1974-12-12

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/80 ,  H01L21/331 ,  H01L21/337 ,  H01L21/762 ,  H01L27/00 ,  H01L29/00 ,  H01L29/73 ,  H01L29/808 ,  H01L29/10

Abstract: A space charge limited transistor formed on a high resistivity substrate of at least 10,000 ohm-centimeter silicon of one conductivity type. One surface of the substrate is provided with spaced recessed oxide regions. The alternate spaces between the oxide regions are occupied by impurity zones of said one conductivity type. The intervening alternate spaces between the oxide regions are occupied by impurity zones of the other conductivity type. The impurity concentrations of the aforesaid impurity zones are at least several orders of magnitude higher than that of the substrate where the zones are separated from each other by the aforesaid oxide regions. The dielectric relaxation time is much larger than the carrier transit time within the substrate below and between adjacent impurity zones of the same conductivity type.

公开(公告)号：BR8104010A

公开(公告)日：1982-03-16

申请号：BR8104010

申请日：1981-06-26

Applicant: IBM

Inventor： MAGDO INGRID E ,  GOTH GEORGE R ,  MALAVIYA SHASHI D

IPC: H01L21/3205 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/336 ,  H01L21/60 ,  H01L29/41 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L27/00

Abstract: A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions and, more particularly self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal or dielectric structure is substantially planar. The method of forming integrated circuits with this structure involves providing a silicon body (50, 51) and then forming a first insulating layer (52) on a major surface of the silicon body. A layer of polycrystalline silicon (53) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer (55) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (56) on the major surface of the silicon body (50). The remaining polycrystalline silicon layer (53) is then removed by etching to leave the narrow dimensioned regions (56) on the major surfaces of the silicon body. A conductive layer is blanket desposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions (56) are reached leaving the structure of patterns (59 to 64) of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less.

公开(公告)号：CA1068011A

公开(公告)日：1979-12-11

申请号：CA250133

申请日：1976-04-13

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN ,  NESTORK WILLIAM J

IPC: H01L27/00 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L23/535 ,  B23P1/00 ,  H01L27/12

Abstract: PROCESS FOR FABRICATING DEVICES HAVING DIELECTRIC ISOLATION AND STRUCTURE. A process for forming complete dielectrically isolated monocrystalline silicon regions on a substrate by depositing a first epitaxial silicon layer embodying an N-type impurity on a low resistivity silicon substrate embodying a P-type impurity, forming annular P-type impurity regions in the first epitaxial layer, depositing the second epitaxial layer embodying an N-type impurity on the first epitaxial layer, forming annular P-type impurity regions in the second epitaxial layer in registry with the annular regions in the first epitaxial layer, converting the silicon substrate and the annular P-type regions in the first and second epitaxial layers into porous silicon material by an anodic treatment carried out in an aqueous solution of hydrofluoric acid, and oxidizing the porous silicon material to form silicon oxide. A semiconductor structure having a backing substrate of silicon oxide with monocrystalline silicon islands embedded therein. A preferred embodiment includes low resistivity regions that extend through the substrate.

公开(公告)号：CA1048659A

公开(公告)日：1979-02-13

申请号：CA247252

申请日：1976-03-02

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L27/04 ,  H01L21/331 ,  H01L21/822 ,  H01L29/73 ,  H01L29/8605 ,  H01L27/02 ,  H01L29/12

Abstract: SEMICONDUCTOR RESISTOR HAVING HIGH VALUE RESISTANCE A semiconductor resistor structure for providing a high value resistance particularly adapted for space charge limited transistor applications, the resistor being fabricated in a semiconductor body having a resistivity in excess of 1 ohm cm., more preferably in semiconductor material that is nearly intrinsic. The resistor has two parallel elongated surface diffused regions in the body of an impurity similar to the background impurity of the body and having a surface concentration sufficient to provide an ohmic contact, the boundaries of said surface diffused regions defined by the interface where the impurity concentration of the diffused region is ten percent more than the impurity concentration of the background impurity of the body. In a preferred embodiment, the surface diffused regions are spaced such that the boundaries intersect with each other, and ohmic contact terminals to each of the diffused regions.

公开(公告)号：CA1000419A

公开(公告)日：1976-11-23

申请号：CA194528

申请日：1974-03-08

Applicant: IBM

Inventor： MAGDO INGRID E

IPC: H01L21/82 ,  H01L27/06 ,  H01L29/00