公开(公告)号：GB2317976A

公开(公告)日：1998-04-08

申请号：GB9716264

申请日：1997-07-31

Applicant: IBM

Inventor： LOPER ALBERT J ,  MALLICK SOUMMYA

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/38 ,  G06F12/08 ,  G06F15/78 ,  G11C7/00

Abstract: While a set-associative cache memory 14, 16 in a processing device 10 operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer number and N>1. While the cache memory operates in a second, power-saving mode, the information is stored in up to M number of ways of the cache memory, where M is an integer number and 0

公开(公告)号：DE69719235D1

公开(公告)日：2003-04-03

申请号：DE69719235

申请日：1997-04-25

Applicant: IBM

Inventor： MALLICK SOUMMYA ,  LOPER ALBERT JOHN

IPC: G06F9/32 ,  G06F9/38

Abstract: A processor (10) and method for speculatively executing branch instructions utilizing a selected branch prediction methodology are disclosed. The processor has one or more execution units (22, 28, 30) for executing instructions, including a branch processing unit (18) for executing branch instructions. The branch processing unit includes selection logic for selecting one of a plurality of branch prediction methodologies and a branch prediction unit for predicting the resolution of a conditional branch instruction utilizing the selected branch prediction methodology. The branch processing unit further includes execution facilities for speculatively executing the conditional branch instruction based upon the prediction. Based upon the outcome of the prediction, the selection logic selects a branch prediction methodology for predicting a subsequent conditional branch instruction so that branch prediction accuracy is enhanced. In one embodiment, the multiple branch prediction methodologies include static and dynamic branch prediction.

公开(公告)号：GB2317975B

公开(公告)日：2001-09-12

申请号：GB9716260

申请日：1997-07-31

Applicant: IBM

Inventor： LOPER ALBERT J ,  MALLICK SOUMMYA

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/312 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0864

Abstract: If a processor 10 is operating in a 'full-power' mode, a load/store unit 28, executing a load instruction directed to floating-point registers 36, loads 64 bits of data from a data cache 16 into a rename buffer 38 during a single processor cycle. If, however, the processor is operating in a 'special' power mode, then the 64 bits are loaded over two cycles instead (i.e. 32 bits per cycle), halving the number of sense amplifiers active at a time in the cache and so saving power. The maximum number of instructions fetched per cycle from an instruction cache 14, decoded and dispatched to execution units 20, 22, 26, 28, and the number of cache ways active at a time, may also be halved in the 'special' power-saving mode.

公开(公告)号：GB2321545B

公开(公告)日：2001-08-01

申请号：GB9724389

申请日：1997-11-19

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  MALLICK SOUMMYA ,  MCDONALD ROBERT G

IPC: G06F9/44 ,  G06F9/48 ,  G06F9/38 ,  G06F9/45

公开(公告)号：GB2321544B

公开(公告)日：2001-08-01

申请号：GB9724351

申请日：1997-11-19

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  MALLICK SOUMMYA ,  MCDONALD ROBERT G

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/48

公开(公告)号：SG64433A1

公开(公告)日：1999-04-27

申请号：SG1997002908

申请日：1997-08-11

Applicant: IBM

Inventor： LOPER ALBERT J ,  MALLICK SOUMMYA

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/312 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0864

Abstract: If a processor 10 is operating in a 'full-power' mode, a load/store unit 28, executing a load instruction directed to floating-point registers 36, loads 64 bits of data from a data cache 16 into a rename buffer 38 during a single processor cycle. If, however, the processor is operating in a 'special' power mode, then the 64 bits are loaded over two cycles instead (i.e. 32 bits per cycle), halving the number of sense amplifiers active at a time in the cache and so saving power. The maximum number of instructions fetched per cycle from an instruction cache 14, decoded and dispatched to execution units 20, 22, 26, 28, and the number of cache ways active at a time, may also be halved in the 'special' power-saving mode.

公开(公告)号：GB2321984A

公开(公告)日：1998-08-12

申请号：GB9725507

申请日：1997-12-02

Applicant: IBM ,  MOTOROLA INC

Inventor： MALLICK SOUMMYA ,  PATEL RAJESH BHIKHUBHAI ,  LOPER ALBERT J ,  JESSANI ROMESH M

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/312

Abstract: A processor includes execution circuitry and a set of registers GPR26-31 which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be transferred to or from a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes it such that at least two data words among the plurality of data words are written to or read from at least two corresponding registers during a single cycle of the processor.

公开(公告)号：GB2317977A

公开(公告)日：1998-04-08

申请号：GB9716265

申请日：1997-07-31

Applicant: IBM

Inventor： LOPER ALBERT J ,  MALLICK SOUMMYA

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F12/08

Abstract: When a processing device 10 operates in a 'special' mode, the maximum number of instructions dispatched by dispatch circuitry in a sequencer unit 18, per cycle of the circuitry, to execution units 20, 22, 26, 28, 30 is reduced to save power. The number of cache ways active at a time in caches 14 and 16 may also be reduced.