公开(公告)号：FI922348A

公开(公告)日：1992-11-29

申请号：FI922348

申请日：1992-05-22

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/38 ,  G06F1/24 ,  G06F13/40

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.

公开(公告)号：CA2067602A1

公开(公告)日：1992-11-29

申请号：CA2067602

申请日：1992-04-29

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERNANDEZ LUIS A ,  MATHISEN ERIC ,  MOELLER DENNIS L ,  RAYMOND JONATHAN H ,  TASHAKORI ESMAEIL

IPC: G06F13/18 ,  G06F13/36 ,  G06F13/362 ,  G06F13/20

Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.

公开(公告)号：MX9202526A

公开(公告)日：1992-11-01

申请号：MX9202526

申请日：1992-05-28

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/362 ,  G06F13/40 ,  G06K9/26

Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.

公开(公告)号：UY23414A1

公开(公告)日：1992-05-27

申请号：UY23414

申请日：1992-05-19

Applicant: IBM

Inventor： FUOCO DANEL P ,  HERNANDEZ LUIS A ,  MOELLER DENNIS L ,  ARAYMOND JONATHAN H ,  TASHAKORI ESMAEIL ,  MATHISEN ERIC

IPC: G06F1/24 ,  G06F9/00 ,  G06F13/00

Abstract: El presente invento se refiere a computadoras personales en las que se proporciona la capacidad para continuar el procesamiento a través de una señal de RESET evitando al mismo tiempo fallas del sistema. El sistema de computadora personal tiene un bus de procesador de datos de alta velocidad; un bus de datos de entrada/salida; un microprocesador reseteable acoplado directamente al bus de procesador local; y un controlador de interfase de bus acoplado directamente al bus de procesador local y directamente al bus de datos de entrada/salida para proporcionar comunicaciones entre el bus de procesador loca y el bus de datos de entrada/salida. El controlador de interfase de bus proporciona arbitraje entre dispositivos acoplados directamente al bus de datos de entrada/salida para acceso al bus de datos de entrada/salida y al bus de procesador local y arbitraje entre el bus de datos de entrada /salida y el microprocesador para acceso al bus de procesador local. El controlador de interfase de bus además reconoce el recibo de una señal de reset destinada a iniciar un reset de microprocesador y difiere la emisión de una señal de reset al microprocesador hasta que el control de interfase de bus haya bloqueado el acceso al bus de procesador local y el bus de entrada/salida por cualquiera de los dispositivos que potencialmente puedan solicitar tal acceso.

公开(公告)号：FI922348A0

公开(公告)日：1992-05-22

申请号：FI922348

申请日：1992-05-22

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASKHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/38 ,  G06F13/40 ,  G06F

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.

公开(公告)号：DE69229656T2

公开(公告)日：2000-03-02

申请号：DE69229656

申请日：1992-05-19

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/00

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.

公开(公告)号：DE69226403T2

公开(公告)日：1999-03-25

申请号：DE69226403

申请日：1992-05-19

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/362 ,  G06F13/40

Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.

公开(公告)号：AT169135T

公开(公告)日：1998-08-15

申请号：AT92304511

申请日：1992-05-19

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/362 ,  G06F13/40

Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.

公开(公告)号：IN179599B

公开(公告)日：1997-10-25

申请号：IN443MA1991

申请日：1991-06-10

Applicant: IBM

Inventor： FUOCO DANIAL PAUL ,  HERNANDEZ LOUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/28

公开(公告)号：AU661480B2

公开(公告)日：1995-07-27

申请号：AU1520192

申请日：1992-04-28

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/38 ,  G06F1/24 ,  G06F13/40 ,  G06F9/00

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.