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    Look-ahead for coded signal processing channels
    21.
    发明专利
    Look-ahead for coded signal processing channels 未知

    公开(公告)号：SG44417A1

    公开(公告)日：1997-12-19

    申请号：SG1996000254

    申请日：1991-05-09

    Applicant: IBM

    Inventor： RUTLEDGE ROBERT A ,  PATEL ARVIND M

    IPC: G11B20/10 ,  G11B20/14 ,  H03M5/14 ,  H03M7/46 ,  H03M7/14 ,  H04L25/49

    Abstract: A signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the values of functional expressions for a baseline check and for a peak-position check. These precomputed values are compared against appropriate thresholds to provide respective binary decision outputs which, with state values corresponding to the current state, are used to determine state values for the next state, which become the current state values for the next iteration of the clock cycle. During each of a series of successive clock cycles, one successive bit of coded binary data corresponding to said current sample value is decoded, and at the next clock cycle, the computed next state becomes the new current state. Sensitivity to missing or extra-bit errors is minimized and full advantage of a (1,7) run-length-limited code constraint is achieved. A phase check is not necessary.

    ERROR DETECTION SYSTEMS
    24.
    发明专利
    ERROR DETECTION SYSTEMS 未知

    公开(公告)号：CA1026865A

    公开(公告)日：1978-02-21

    申请号：CA185970

    申请日：1973-11-16

    Applicant: IBM

    Inventor： MCDONALD EARL G JR ,  PATEL ARVIND M

    IPC: G06F12/16 ,  G06F11/10 ,  G11B20/18 ,  H03M13/00

    Abstract: Error detection is enhanced by using multiple independent error codes combined with nonlinear changes in the data field as applied to different error codes. Such nonlinear permutations increase the probability of detecting errors thereby maximizing the utilization of check bit redundancies. In a magnetic tape subsystem, error detection and correction can be enhanced by scrambling track-to-error code relationships between a plurality of independent codes. Tracks with the highest probability of errors, i.e., the outside tracks on a 1/2 inch tape, for example, are connected to nonadjacent inputs of error correction code apparatus. Additionally, the input-to-track relationship of various code apparatus can be scrambled, either permanently or during a tape transducing operation. The above permutations provide best advantage with selected error correction codes and systems having identifiable probability of error patterns.

    ARCHIVAL DATA PROTECTION
    25.
    发明专利
    ARCHIVAL DATA PROTECTION 未知

    公开(公告)号：CA1014664A

    公开(公告)日：1977-07-26

    申请号：CA198776

    申请日：1974-05-02

    Applicant: IBM

    Inventor： BOSSEN DOUGLAS C ,  HSIAO MU-YUE ,  PATEL ARVIND M

    IPC: G06F12/16 ,  G06F11/10 ,  G11B20/18 ,  H03M13/00

    Abstract: 1440285 Error correction INTERNATIONAL BUSINESS MACHINES CORP 24 April 1974 [4 June 1973] 18002/74 Heading G4A Data is stored on a plurality of independently accessible storage units, e.g. magnetic tape cartridges, and check bits, each of which is a function of a corresponding bit from each data storage unit, are stored on a check unit which may be used, in the event of a catastrophic loss of data on one of the data storage units and detected by an error checking facility associated with that unit, to restore the data on that unit. Extension of the system to include more than one check unit, each of which stores the check bits for one position of a Hamming code, is also mentioned. In normal operation, one of the data storage units is selected and data thereon is updated by read before write heads 15, 21. The difference e jk between each old bit and the corresponding new bit is EXORed with the corresponding old parity bit p k from the check unit to update the parity bits. The parity bits are initially recorded by successively (or simultaneously) reading the data storage units to record the modulo 2 sums of the corresponding bits, and data restoration is similar reading from the good data storage units and the check unit.

    SYNDROME PROCESSING UNIT FOR MULTIBYTE ERROR CORRECTING SYSTEM
    28.
    发明专利
    SYNDROME PROCESSING UNIT FOR MULTIBYTE ERROR CORRECTING SYSTEM 未知

    公开(公告)号：CA1199411A

    公开(公告)日：1986-01-14

    申请号：CA438448

    申请日：1983-10-05

    Applicant: IBM

    Inventor： PATEL ARVIND M

    IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15

    Abstract: SYNDROME PROCESSING UNIT FOR MULTIBYTE ERROR CORRECTING SYSTEMS A syndrome processing unit for a multibyte error correcting system is disclosed in which logical circuitry for performing product operation on selected pairs of 8-bit syndrome bytes and exclusive-OR operations on selected results of the product operations are selectively combined to define usable cofactors that correspond to coefficients of an error locator polynomial corresponding to a selected codeword if the codeword contains less than the maximum number of errors for which the system has been designed.

    DUAL FUNCTION ERROR CORRECTING SYSTEM
    29.
    发明专利
    DUAL FUNCTION ERROR CORRECTING SYSTEM 未知

    公开(公告)号：CA1159959A

    公开(公告)日：1984-01-03

    申请号：CA385497

    申请日：1981-09-09

    Applicant: IBM

    Inventor： PATEL ARVIND M

    IPC: H03M13/19 ,  G06F11/10 ,  G06F11/08

    Abstract: SA980033 DUAL FUNCTION ERROR CORRECTING SYSTEM A dual function cyclic code error correcting method and system are disclosed for correcting from a single syndrome byte a random single-bit error which occurs in a multi-byte data word or, alternatively, correcting a multi-bit error in one byte of the data word by providing an indication of the location of the byte in error, and employing the same syndrome byte to determine the error pattern of the multi-bit error so the multi-bit error can be corrected. The method involves non-zero syndrome processing steps which comprise a first series of steps which function to determine if the non-zero syndrome correlates to a 1-bit error in one of the byte positions of the data word being protected, and if so, to automatically correct the single-bit error by processing the entire byte containing the single-bit error. If no correlation of the syndrome byte is established with a singlebit error, then the byte position in the data word of the multi-bit error is used during a second series of steps to process the same non-zero syndrome byte to determine the pattern of the multi-bit error in the defective byte so that the pattern can be employed to correct the defective byte. The method and apparatus disclosed also identify the location of repetitive multi-byte errors by generating a byte parity vector for each data word and using these byte parity vectors to identify the location in each data word of repetitive errors of the multi-bit type.

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