公开(公告)号：DE68906095D1

公开(公告)日：1993-05-27

申请号：DE68906095

申请日：1989-06-29

Applicant: IBM

Inventor： AKBAR SHAH ,  KROESEN PATRICIA LAVELLE ,  OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L29/73 ,  G03C3/00 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L29/72 ,  H01L29/52 ,  H01L29/60

Abstract: A Compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer (12); a base layer (14) disposed over the collector layer; an emitter layer (16) disposed over the base layer; a first sidewall insulating layer (18) disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer (20) disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer (22) formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer. The structure further includes a base contact interconnect (24) disposed on a surface of the base contact extension layer and; a collector contact extension layer (26) formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect (29) disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers.

公开(公告)号：BR8700839A

公开(公告)日：1987-12-22

申请号：BR8700839

申请日：1987-02-23

Applicant: IBM

Inventor： DALLY ANTHONY JOHN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/312 ,  H01L29/94

Abstract: A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

公开(公告)号：DE60103181T2

公开(公告)日：2005-05-04

申请号：DE60103181

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHEN A ,  HIRSCH ALEXANDER ,  IYER UMAR ,  ROVEDO NIVO ,  WANN HSING-JEN ,  ZHANG YING

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

公开(公告)号：DE102004016700A1

公开(公告)日：2004-11-18

申请号：DE102004016700

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEHAVEN PATRICK W ,  AGNELLO PAUL D ,  WONG KEITH KWONG HON ,  HUANG HSIANG-JEN ,  MURPHY RICHARD J ,  DZIOBKOWSKI CHET ,  CLEVENGER LAWRENCE ,  LAVOIE CHRISTIAN ,  ROVEDO NIVO ,  FANG SUNFEI

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

公开(公告)号：DE69302960T2

公开(公告)日：1996-12-12

申请号：DE69302960

申请日：1993-03-23

Applicant: IBM

Inventor： DOERRE GEORGE WILLIAM ,  OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84 ,  H01L21/302

Abstract: An SOI wafer (10/20) has an epitaxial device layer (30) of initial thickness that is formed into a set of mesas (40) in the interval between which a temporary layer (42) of polysilicon is blanket deposited to a precisely controlled thickness. This polysilicon is entirely converted in a self-limiting process to an oxide etch stop pads (45) (having a thickness greater than the initial thickness) except on the mesa side walls. The mesas are thinned by a chemical mechanical polishing technique until the mesa is the same level as the top surface of the new oxide. The etch stop layer of oxide forming pads (45) is not removed but serves both as an isolating layer to provide dielectric isolation between final mesas (40') in the final circuit and also as a visual gauge to determine the time when the polishing process should stop.

公开(公告)号：DE68926224T2

公开(公告)日：1996-10-10

申请号：DE68926224

申请日：1989-11-07

Applicant: IBM

Inventor： OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L21/82

Abstract: A method for fabricating a Bi-CMOS device including both vertical PNP and NPN components. The process steps include forming the reach-through N+ subcollector to the bipolar device without extra processing steps; combining into one mask the threshold adjust/well implants with self-aligned isolation leakage protection implants by using a self-aligned, removable oxide mask prior to field isolation; using a resist etch-back scheme to protect against emitter-to-base punch-through while self-aligning the pedestal and base; and also providing for the removal of the gate oxide at the emitter while maintaining it at the FET, without extra masks. The device incorporates similar structural features between the bi-polar and FET devices. The NPN and PFET can share the same well and a P+ diffusion (the P+ extrinsic base is the same as the P+ source). Also, the PNP and NFET can share the same well and an N+ diffusion.

公开(公告)号：DE68926224D1

公开(公告)日：1996-05-15

申请号：DE68926224

申请日：1989-11-07

Applicant: IBM

Inventor： OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L21/82

Abstract: A method for fabricating a Bi-CMOS device including both vertical PNP and NPN components. The process steps include forming the reach-through N+ subcollector to the bipolar device without extra processing steps; combining into one mask the threshold adjust/well implants with self-aligned isolation leakage protection implants by using a self-aligned, removable oxide mask prior to field isolation; using a resist etch-back scheme to protect against emitter-to-base punch-through while self-aligning the pedestal and base; and also providing for the removal of the gate oxide at the emitter while maintaining it at the FET, without extra masks. The device incorporates similar structural features between the bi-polar and FET devices. The NPN and PFET can share the same well and a P+ diffusion (the P+ extrinsic base is the same as the P+ source). Also, the PNP and NFET can share the same well and an N+ diffusion.

公开(公告)号：DE3784958T2

公开(公告)日：1993-09-30

申请号：DE3784958

申请日：1987-01-23

Applicant: IBM

Inventor： DALLY ANTHONY JOHN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/78 ,  H01L21/225

Abstract: A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

公开(公告)号：AU6995987A

公开(公告)日：1987-09-24

申请号：AU6995987

申请日：1987-03-12

Applicant: IBM

Inventor： DALLY ANTHONY JOHN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/762

Abstract: A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

公开(公告)号：SG151256A1

公开(公告)日：2009-04-30

申请号：SG2009016890

申请日：2006-09-15

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： WAY TEH YOUNG ,  SUNFEI FANG ,  ZHIJIONG LUO ,  NG HUNG Y ,  ROVEDO NIVO ,  JUNG KIM JUN

Abstract: DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200[err]C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET. (Figure 6)