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公开(公告)号：AU569315B2
公开(公告)日：1988-01-28
申请号：AU3180084
申请日：1984-08-10
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , RACKLEY DARWIN PRESTON , SAENZ JESUS ANDRES
Abstract: @ A raster scan display system includes a plurality of storage maps (MAPO to MAP4). These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide colour signals from which colour video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.
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公开(公告)号：AU566038B2
公开(公告)日：1987-10-08
申请号：AU3137484
申请日：1984-08-01
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , SAENZ JESUS ANDRES , TRYNOSKY STEPHEN WAYNE
Abstract: In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.
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公开(公告)号：DE3267005D1
公开(公告)日：1985-11-28
申请号：DE3267005
申请日：1982-06-29
Applicant: IBM
Inventor： EGGEBRECHT LEWIS CLARK , SAENZ JESUS ANDRES
Abstract: A serial keyboard interface (28) connects a self scanning programmable serialized keyboard (40) to the system bus (10) of a data processing system. A cable (42) containing only a clock wire (52) and a data wire (58) provides the connection. The keyboard transmits a 9-bit scan out code consisting of a start bit followed by eight serial data bits. The keyboard clock line (52) is connected to the clock or shift terminal of a serial-to-parallel shift register encoder (62) for shifting the data bits on data line (58) into the encoder which has eight parallel output data lines (A, B . . . G, H) connected to the system bus. When the encoder (62) contains a complete scan out frame, the start bit is in the most significant stage (h') and sets the D-type latch (68) to apply a CPU interrupt request to the system bus (10). At this time, the &upbar& Q output of latch (68) pulls down the data line to ground potential, thereby disabling the data line and preventing further keyboard transmission of data. When the interrupt request is granted by the CPU, a clear signal resets latch (68) to remove ground potential from data line (58) and thereby permit further transmission of data.
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公开(公告)号：BR8404080A
公开(公告)日：1985-07-16
申请号：BR8404080
申请日：1984-08-15
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , SAENZ JESUS ANDRES , TRYNOSKY STEPHEN WAYNE
Abstract: In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.
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公开(公告)号：BR8403987A
公开(公告)日：1985-07-09
申请号：BR8403987
申请日：1984-08-09
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , RACKLEY DARWIN PRESTON , SAENZ JESUS ANDRES
Abstract: @ A raster scan display system includes a plurality of storage maps (MAPO to MAP4). These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide colour signals from which colour video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.
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Patent Agency Ranking
公开(公告)号：HK9591A
公开(公告)日：1991-02-08
申请号：HK9591
申请日：1991-01-31
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , RACKLEY DARWIN PRESTON , SAENZ JESUS ANDRES
Abstract: @ A raster scan display system includes a plurality of storage maps (MAPO to MAP4). These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide colour signals from which colour video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.
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公开(公告)号：HK54790A
公开(公告)日：1990-07-27
申请号：HK54790
申请日：1990-07-19
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , SAENZ JESUS ANDRES , TRYNOSKY STEPHEN WAYNE
IPC: G09G5/00 , G06F3/00 , G06F3/14 , G06F7/02 , G06T7/00 , G09G1/16 , G09G5/02 , G09G5/393 , G09G5/395 , G06F15/70
Abstract: In a bit mapped raster scan digital display system, a number of maps (MAPO-MAP3), each contain a single component of the display data and are read together to provide sets of bytes, each set representing eight pel defining groups. A compare system is provided for determining when a pel group in a set of bytes compares with a reference pel defining group. For the, or each, pair of maps, the compare system compares each bit of the two bytes of data with the correspondingly positioned bit of the reference group to provide outputs when a corresponding bit in each of the bytes compares with the two reference bits. When more than two maps are employed the compare outputs related to all of the pairs of maps are combined to provide an output signal when a pel group in a byte from the maps compares with the reference bits. In a modification of the system, the comparison can be made between one or more of the maps and the corresponding bit or bits of the compare data.
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公开(公告)号：HK23890A
公开(公告)日：1990-04-06
申请号：HK23890
申请日：1990-03-29
Applicant: IBM
Inventor： RACKLEY DARWIN PRESTON , SAENZ JESUS ANDRES , YOSIM PAUL STEWART
IPC: G09G5/18 , G06F3/153 , G09G1/16 , G09G1/28 , G09G5/00 , G09G5/02 , G09G5/04 , G09G5/36 , H04N3/27
Abstract: A digital display system includes a monitor arranged to receive digital display data and synchronising signals to develop displays on a cathode ray tube. The monitor is switched between different line structure and/or colour definition modes in response to the polarity of one of the vertical or horizontal synchronising signals trains. A circuit receives this train to provide control signals to the horizontal time base and/or a colour signal code converter. The time base control signal, in accordance with its binary value, controls the frequency of the time base. The colour converter, in response to the control signals, either passes colour signals received in parallel over six input lines without change to the cathode ray tube drive circuits or converts colour signals on four of the input lines to output signals on the six lines to the drive circuits.
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公开(公告)号：AU567569B2
公开(公告)日：1987-11-26
申请号：AU3022684
申请日：1984-07-03
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , SAENZ JESUS ANDRES , TRYNOSKY STEPHEN WAYNE
IPC: G09G5/00 , G06F3/00 , G06F3/14 , G06F7/02 , G06T7/00 , G09G1/16 , G09G5/02 , G09G5/393 , G09G5/395 , G06F3/153
Abstract: In a bit mapped raster scan digital display system, a number of maps (MAPO-MAP3), each contain a single component of the display data and are read together to provide sets of bytes, each set representing eight pel defining groups. A compare system is provided for determining when a pel group in a set of bytes compares with a reference pel defining group. For the, or each, pair of maps, the compare system compares each bit of the two bytes of data with the correspondingly positioned bit of the reference group to provide outputs when a corresponding bit in each of the bytes compares with the two reference bits. When more than two maps are employed the compare outputs related to all of the pairs of maps are combined to provide an output signal when a pel group in a byte from the maps compares with the reference bits. In a modification of the system, the comparison can be made between one or more of the maps and the corresponding bit or bits of the compare data.
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公开(公告)号：GB2162026A
公开(公告)日：1986-01-22
申请号：GB8513016
申请日：1985-05-23
Applicant: IBM
Inventor： RACKLEY DARWIN PRESTON , SAENZ JESUS ANDRES , YOSIM PAUL STEWART
IPC: G09G5/18 , G06F3/153 , G09G1/16 , G09G1/28 , G09G5/00 , G09G5/02 , G09G5/04 , G09G5/36 , H04N3/27
Abstract: A digital display system includes a monitor arranged to receive digital display data and synchronising signals to develop displays on a cathode ray tube. The monitor is switched between different line structure and/or colour definition modes in response to the polarity of one of the vertical or horizontal synchronising signals trains. A circuit receives this train to provide control signals to the horizontal time base and/or a colour signal code converter. The time base control signal, in accordance with its binary value, controls the frequency of the time base. The colour converter, in response to the control signals, either passes colour signals received in parallel over six input lines without change to the cathode ray tube drive circuits or converts colour signals on four of the input lines to output signals on the six lines to the drive circuits.
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