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    Register context restoration based on rename register recovery
    21.
    发明专利
    Register context restoration based on rename register recovery 未知

    公开(公告)号：GB2575412B

    公开(公告)日：2021-10-20

    申请号：GB201916132

    申请日：2018-03-13

    Applicant: IBM

    Inventor： MICHAEL KARL GSCHWIND ,  CHUNG-LUNG SHUM ,  TIMOTHY SLEGEL ,  VALENTINA SALAPURA

    IPC: G06F9/38

    Abstract: A load request to restore a plurality of architected registers is obtained. Based on obtaining the load request, one or more architected registers of the plurality of architected registers are restored. The restoring uses a snapshot that maps architected registers to physical registers to replace one or more physical registers currently assigned to the one or more architected registers with one or more physical registers of the snapshot corresponding to the one or more architected registers.

    instrução para computar a distância para uma fronteira de memória específica
    22.
    发明专利
    instrução para computar a distância para uma fronteira de memória específica 未知

    公开(公告)号：BR112014022726A2

    公开(公告)日：2021-07-27

    申请号：BR112014022726

    申请日：2012-11-15

    Applicant: IBM

    Inventor： CHRISTIAN JACOBI ,  ERIC MARK SCHWARZ ,  JONATHAN DAVID BRADBURY ,  MICHAEL KARL GSCHWIND ,  TIMOTHY SLEGEL

    IPC: G11C11/00

    Abstract: instrução para computar a distância para uma fronteira de memória específica. é fornecida uma instrução de contagem de carga para limite de bloco que fornece uma distância a partir de um endereço especificado de memória para um limite especificado de memória. o limite de memória é um limite que não deve ser cruzado durante o carregamento de dados. o limite pode ser especificado de várias maneiras, incluindo, mas não limitado a, um valor variável no texto de instrução, um valor de texto de instrução fixo codificado no código de operação ou um limite baseado em registro; ou pode ser dinamicamente determinado.

    Comparing sets of character data having termination characters
    24.
    发明专利
    Comparing sets of character data having termination characters 未知

    公开(公告)号：GB2514062B

    公开(公告)日：2019-08-28

    申请号：GB201415053

    申请日：2013-03-01

    Applicant: IBM

    Inventor： JONATHAN DAVID BRADBURY ,  MICHAEL KARL GSCHWIND ,  TIMOTHY SLEGEL

    IPC: G06F9/30 ,  G06F7/02 ,  G06V30/224 ,  G06F17/22

    Abstract: Multiple sets of character data having termination characters are compared using parallel processing and without causing unwarranted exceptions. Each set of character data to be compared is loaded within one or more vector registers. In particular, in one embodiment, for each set of character data to be compared, an instruction is used that loads data in a vector register to a specified boundary, and provides a way to determine the number of characters loaded. Further, an instruction is used to find the index of the first delimiter character, i.e., the first zero or null character, or the index of unequal characters. Using these instructions, a location of the end of one of the sets of data or a location of an unequal character is efficiently provided.

    Prioritization of transactions
    25.
    发明专利
    Prioritization of transactions 未知

    公开(公告)号：GB2562014B

    公开(公告)日：2019-04-03

    申请号：GB201813750

    申请日：2017-01-12

    Applicant: IBM

    Inventor： ERIC MARK SCHWARZ ,  FADI YUSUF BUSABA ,  MICHAEL KARL GSCHWIND ,  TIMOTHY SLEGEL ,  VALENTINA SALAPURA ,  HAROLD WADE III CAIN

    IPC: G06F9/46

    Abstract: A method, system, and computer program product are provided for prioritizing transactions. A processor in a computing environment initiates the execution of a transaction. The processor includes a transactional core, and the execution of the transaction is performed by the transactional core. The processor obtains concurrent with the execution of the transaction by the transactional core, an indication of a conflict between the transaction and at least one other transaction being executed by an additional core in the computing environment. The processor determines if the transactional core includes an indicator and based on determining that the transactional core includes an indicator, the processor ignores the conflict and utilizing the transactional core to complete executing the transaction.

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