公开(公告)号：JP2008172237A

公开(公告)日：2008-07-24

申请号：JP2008001329

申请日：2008-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  LUO ZHIJIONG

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/08 ,  H01L27/092 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To form fully silicided dual gates on fins of a FinFET device by correctly controlling a thickness of remaining polysilicon gates using a CMP method.
SOLUTION: A method for forming a fully silicided gate on the each fin of a FinFET device includes steps of: pattern-forming a gate stack consisting of a polysilicon layer and a polysilicon germanium layer on the each fin; removing the polysilicon germanium layer on one of the fins; forming a metal layer on the each fin; and forming the fully silicided gate on the each fin of the FinFET by annealing the FinFET device.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：通过使用CMP方法正确地控制剩余多晶硅栅极的厚度，在FinFET器件的鳍片上形成完全硅化的双栅极。 解决方案：在FinFET器件的每个鳍上形成全硅化栅的方法包括以下步骤：在每个鳍上形成由多晶硅层和多晶硅锗层组成的栅叠层; 去除其中一个翅片上的多晶硅锗层; 在每个翅片上形成金属层; 以及通过对FinFET器件进行退火，在FinFET的每个鳍上形成完全硅化的栅极。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008131032A

公开(公告)日：2008-06-05

申请号：JP2007266424

申请日：2007-10-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG

IPC: H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1037 ,  H01L29/6659

Abstract: PROBLEM TO BE SOLVED: To provide a CMOS device having a semiconductor substrate region of a plurality of crystal orientations, a CMOS structure, and a method of manufacturing such a CMOS device and a CMOS structure.
SOLUTION: The CMOS structure includes a first device arranged using a first active region in a semiconductor substrate. The first active region is flat and has a first crystal orientation. The CMOS structure also includes a second device arranged using a second active region in the semiconductor substrate. The second active region is in a three-dimensional shape and has a second crystal orientation in which the first crystal orientation does not exist. The first and second crystal orientations can optimize performance in the first and second devices regarding charge carrier mobility typically. The second active region in a three-dimensional shape also has a uniform thickness. The CMOS structure can be manufactured by crystallographically specific etchant for forming the second active region in a three-dimensional shape.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有多个晶体取向的半导体衬底区域的CMOS器件，CMOS结构以及制造这种CMOS器件和CMOS结构的方法。 解决方案：CMOS结构包括使用半导体衬底中的第一有源区布置的第一器件。 第一有源区域是平坦的并且具有第一晶体取向。 CMOS结构还包括使用半导体衬底中的第二有源区布置的第二器件。 第二活性区域是三维形状并且具有其中不存在第一晶体取向的第二晶体取向。 第一和第二晶体取向可以优化第一和第二器件中关于电荷载流子迁移率的性能。 三维形状的第二活性区域也具有均匀的厚度。 CMOS结构可以通过晶体学上特定的蚀刻剂制造，以形成三维形状的第二有源区。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007300090A

公开(公告)日：2007-11-15

申请号：JP2007106817

申请日：2007-04-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  YANG DAEWON

IPC: H01L21/8238 ,  H01L21/768 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L21/31116 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

Abstract: PROBLEM TO BE SOLVED: To provide a structure applying mechanical stress in a CMOS structure for improving device performance and the yield of chips, and a method therefor. SOLUTION: The invention relates to a CMOS structure and a method for manufacturing the CMOS structure, in which a first stressed layer arranged on a first transistor and a second stressed layer on a second transistor are contacted but are not overlapped to each other. With such contact that is not overlapped, flexibility in manufacturing is improved when forming the contact to a silicide layer on a source/a drain region in one of the first and the second transistor. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在CMOS结构中应用机械应力以提高器件性能和芯片产量的结构及其方法。 解决方案：本发明涉及CMOS结构和制造CMOS结构的方法，其中布置在第一晶体管上的第一应力层和第二晶体管上的第二应力层接触但不彼此重叠 。 通过不重叠的接触，当形成与第一和第二晶体管中的一个的源极/漏极区域上的硅化物层的接触时，制造中的柔性得到改善。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007142400A

公开(公告)日：2007-06-07

申请号：JP2006303402

申请日：2006-11-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  DORIS BRUCE B ,  JIN WAN ,  REN ZHIBIN

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

Abstract: PROBLEM TO BE SOLVED: To provide a structure having the superposition of stressed layers bringing a compressive stress into the channel of a p-type MOSFET device and a tensile stress into the channel of an n-type MOSFET device on each gate stack and including the p-type MOSFET device and the n-type MOSFET device that are adjacent, and to provide a method of manufacturing the same. SOLUTION: One of a p-type MOSFET device or an n-type MOSFET device has a height shorter than that of the other adjacent device, and the boundary of the shorter device of the two devices is defined by a discontinuity, i.e. an opening part in the stressed layers superposed on the shorter device. In a preferable method for forming the device, a single stressed layer is formed on the gate stack having different heights for forming a first type stress in the substrate under the gate stack. An opening part is formed in the stressed layer at a distance from the shorter gate stack, so that a second type stress is formed under the shorter gate stack. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种结构，其具有将压应力叠加在p型MOSFET器件的沟道中的应力层和在每个栅极堆叠上的n型MOSFET器件的沟道中的拉伸应力的结构 并且包括相邻的p型MOSFET器件和n型MOSFET器件，并且提供其制造方法。 解决方案：p型MOSFET器件或n型MOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件的较短器件的边界由不连续性定义，即 应力层中的开口部分叠加在较短的装置上。 在用于形成该器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极叠层下的衬底中形成第一类型应力。 在距离较短栅极堆叠一定距离处的应力层中形成开口部分，使得在较短的栅极堆叠下形成第二类型的应力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007123892A

公开(公告)日：2007-05-17

申请号：JP2006290437

申请日：2006-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1207

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure having improved practicality, and a method for fabricating the semiconductor structure. SOLUTION: The semiconductor structure and its method for fabrication include a first surface semiconductor layer of a first crystallographic orientation located upon a dielectric surface of a substrate. Located laterally separated upon the dielectric surface from the first surface semiconductor layer is a stack layer. The stack layer includes a buried semiconductor layer located nearer the dielectric surface, and a second surface semiconductor layer of a second crystallographic orientation different from the first crystallographic orientation located over and not contacting the buried semiconductor layer. The semiconductor structure provides a pair of semiconductor surface regions of different crystallographic orientation. A particular embodiment may be fabricated utilizing a sequential laminating, patterning, selective stripping and selective epitaxial deposition method. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有改进的实用性的半导体结构以及制造半导体结构的方法。 解决方案：半导体结构及其制造方法包括位于基板的电介质表面上的第一晶体取向的第一表面半导体层。 在第一表面半导体层的电介质表面上横向分离的是堆叠层。 堆叠层包括位于电介质表面附近的掩埋半导体层，以及不同于位于掩埋半导体层之上并且不接触掩埋半导体层的第一晶体取向的第二晶体取向的第二表面半导体层。 半导体结构提供了一对具有不同晶体取向的半导体表面区域。 可以使用顺序层压，图案化，选择性剥离和选择性外延沉积方法来制造特定实施例。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：SG155176A1

公开(公告)日：2009-09-30

申请号：SG2009051418

申请日：2007-05-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： ZHU HUILONG ,  LUO ZHIJIONG ,  CHONG YUNG FU ,  TESSIER BRIAN LEE

Abstract: Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of the gate, allowing stress retained by the gate to be transferred to the channel; replacing (or refilling) the gate with a replacement gate; and removing the intrinsically stressed material. Removing and replacing the gate allows stress retained by the original gate to be transferred to the channel, with the replacement gate maintaining (memorizing) that situation. The methods do not damage the gate dielectric. A structure may include a transistor having a channel including a first stress that is one of a compressive and tensile and a gate including a second stress that is the other of compressive and tensile.

公开(公告)号：SG137804A1

公开(公告)日：2007-12-28

申请号：SG2007036031

申请日：2007-05-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： ZHU HUILONG ,  LUO ZHIJIONG ,  CHONG YUNG FU ,  TESSIER BRIAN LEE

Abstract: Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material (130) over the transistor (102A, 102B) including a gate (110) thereof; removing a portion of the intrinsically stressed material (130) over the gate (110); removing at least a portion of the gate (110), allowing stress retained by the gate (110) to be transferred to the channel; replacing (or refilling) the gate (110) with a replacement gate (160); and removing the intrinsically stressed material. Removing and replacing the gate (110) allows stress retained by the original gate (110) to be transferred to the channel, with the replacement gate (160) maintaining (memorizing) that situation. The methods do not damage the gate dielectric. A structure may include a transistor having a channel including a first stress that is one of a compressive and tensile and a gate including a second stress that is the other of compressive and tensile.

公开(公告)号：AT535941T

公开(公告)日：2011-12-15

申请号：AT07710010

申请日：2007-01-09

Applicant: IBM

Inventor： ZHU HUILONG

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11

Abstract: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate layer situated over the first gate layer. The contact line includes a height that is less than a combined height of the first gate layer and the subsequent gate layer(s). The MOSFET circuits further include gate spacers situated proximate the gate layers and a single contact line spacer situated proximate the contact line. The gate spacers are taller and thicker than the contact line spacer.

公开(公告)号：SG132641A1

公开(公告)日：2007-06-28

申请号：SG2006081376

申请日：2006-11-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： LUO ZHIJIONG ,  CHONG YUNG FU ,  ZHU HUILONG

Abstract: There is provided a method of manufacturing a field effect transistor (FET) (100) that includes the steps of forming a gate structure (175) on a semiconductor substrate (105), and forming a recess (160) in the substrate and embedding a second semiconductor material (165) in the recess. The gate structure includes a gate dielectric layer (115), conductive layers (120, 130) and an insulating layer (125). Forming said gate structure includes a step of recessing the conductive layer (130) in the gate structure, and the steps of recessing the conductive layer and forming the recess (160) in the substrate are performed in a single step. There is also provided a FET device.

公开(公告)号：AT487234T

公开(公告)日：2010-11-15

申请号：AT05853786

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .