公开(公告)号：EP1825509A4

公开(公告)日：2009-04-15

申请号：EP05853786

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

公开(公告)号：EP1834350A4

公开(公告)日：2009-06-17

申请号：EP05853245

申请日：2005-12-08

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

公开(公告)号：EP1979941A4

公开(公告)日：2011-03-23

申请号：EP07710010

申请日：2007-01-09

Applicant: IBM

Inventor： ZHU HUILONG

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11

CPC classification number: H01L21/28052 ,  H01L21/76889 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S257/92 ,  H01L2924/00

公开(公告)号：JP2008131038A

公开(公告)日：2008-06-05

申请号：JP2007278110

申请日：2007-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  LIANG QINGQING

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/41766 ,  H01L21/26506 ,  H01L21/743 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/78612 ,  H01L29/78684

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for reducing a floating body effect in a metal oxide semiconductor field effect transistor (MOSFET) including a silicon-on-insulator (SOI) device. SOLUTION: A field effect transistor (FET) device includes: a bulk substrate; a gate insulating layer formed on the bulk substrate; source and drain regions that are formed in an active device region relating to the bulk substrate and demarcate a p/n junction section to the body region of the active device region each; and a conductive plug that is demarcated in the source region and is created within a cavity which crosses the p/n junction section in the source region and reaches the inside of the body region. In this case, the conductive plug promotes the discharge path between the body and source regions. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供一种减少包括绝缘体上硅（SOI）器件的金属氧化物半导体场效应晶体管（MOSFET）中的浮体效应的方法和结构。 场效应晶体管（FET）装置包括：体基板; 形成在本体基板上的栅极绝缘层; 源极和漏极区域，其形成在与本体衬底相关的有源器件区域中，并且将p / n结部分划分到每个有源器件区域的体区; 以及导电插塞，其在源极区域中划定并且在与源极区域中的p / n结部分交叉并到达身体区域的内部的空腔内产生。 在这种情况下，导电插塞促进主体和源极区域之间的放电路径。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：EP1856725A4

公开(公告)日：2009-01-14

申请号：EP06717971

申请日：2006-01-10

Applicant: IBM

Inventor： LUO ZHIJIONG ,  FANG SUNFEI ,  ZHU HUILONG

IPC: H01L21/336 ,  H01L29/76

CPC classification number: H01L29/4975 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7833

Abstract: A process for forming a metal silicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (3) (polysilicon or amorphous silicon) is formed overlying the gate dielectric (2); a layer of metal (4) is then formed on the first layer (3), and a second layer of silicon (5) on the metal layer (4). A high-temperature (greater than 700 0C) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer (30) above the gate dielectric (2) by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer (50) from silicon in the second layer (5). The thicknesses of the layers are such that in the high-temperature processing, substantially all the first layer and at least a portion of the second layer are replaced by silicide material. Accordingly, a fully suicided gate structure may be produced.

公开(公告)号：WO2006065759A3

公开(公告)日：2007-06-14

申请号：PCT/US2005044957

申请日：2005-12-13

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

Abstract translation: 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠 所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：JP2008141177A

公开(公告)日：2008-06-19

申请号：JP2007274832

申请日：2007-10-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  TAN YUE

IPC: H01L21/8244 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor configuration comprising a triple gate finFET and a double gate finFET both of which have different vertical dimensions, and to provide a method of fabricating the same. SOLUTION: Implant species comprising germanium is implanted in a bottom portion 33 of selected semiconductor fins 13' on which reduced vertical dimension is desired. The bottom portion 33 of the selected semiconductor fins 13' with implant species is selectively etched to a semiconductor material without the implanted species, that is, the semiconductor material in the top portion 23 of the semiconductor fin and other semiconductor fins 13 without the implanted species, thereby obtaining: finFETs with the full vertical dimension fins and a high on-current; and finFETs with reduced vertical dimension fins with a low on-current, on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins can be adjusted in selected finFETs. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供包括具有不同垂直尺寸的三栅极finFET和双栅极finFET的半导体结构，并提供其制造方法。 解决方案：将包含锗的植入物植入植入需要减小垂直尺寸的所选择的半导体鳍片13'的底部33中。 具有注入物种的所选择的半导体鳍片13'的底部33被选择性地蚀刻到半导体材料上，而没有注入的物质，即半导体鳍片的顶部23中的半导体材料和没有植入物质的其它半导体鳍片13 ，从而获得：具有全垂直尺寸鳍片和高导通电流的finFET; 和在相同的半导体衬底上具有较低导通电流的具有减小的垂直尺寸散热片的finFET。 通过调整植入物种的深度，可以在选定的finFET中调节半导体鳍片的垂直尺寸。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007142391A

公开(公告)日：2007-06-07

申请号：JP2006294964

申请日：2006-10-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG

IPC: H01L29/786

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/7833 ,  H01L29/7848

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure having high mobility of electrons and holes in a doping region, and to provide a method for manufacturing it.
SOLUTION: The present provides a structure and a method for forming the same. The semiconductor structure comprises (a) a substrate having a top substrate surface, (b) a channel region on the top substrate surface, (c) a gate dielectric region on the top substrate surface, and (d) a gate electrode region on the top substrate surface. The channel region is electrically separated from the gate electrode region by the gate dielectric region. The semiconductor structure includes first and second source/drain regions on the top substrate surface. The channel region is arranged between the first and second source/drain regions. The channel region and the gate dielectric regions are directly and physically brought into contact with each other with an interface practically perpendicular to the top substrate surface between. Each of the first and second source/drain regions includes a crystal material, having a lattice constant and a gap different from that in the channel region.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供在掺杂区域中电子和空穴的高迁移率的半导体结构，并提供其制造方法。 解决方案：本发明提供一种用于形成它的结构和方法。 半导体结构包括（a）具有顶部衬底表面的衬底，（b）顶部衬底表面上的沟道区，（c）顶部衬底表面上的栅极介电区，以及（d）栅极电极区 顶部衬底表面。 沟道区域通过栅极电介质区域与栅电极区域电分离。 半导体结构包括在顶部衬底表面上的第一和第二源极/漏极区域。 沟道区布置在第一和第二源/漏区之间。 通道区域和栅极电介质区域之间直接和物理地彼此接触，其界面实质上垂直于顶部衬底表面之间。 第一和第二源极/漏极区域中的每一个包括具有不同于沟道区域中的晶格常数和间隙的晶体材料。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2013179343A

公开(公告)日：2013-09-09

申请号：JP2013105310

申请日：2013-05-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： ZHU HUILONG ,  TAN YUE

IPC: H01L21/8244 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure including a triple gate FinFET and a double gate FinFET having fins of different vertical dimension, and to provide a manufacturing method of a semiconductor structure.SOLUTION: An injection chemical species containing germanium is injected into the bottom part 33 of a selected semiconductor fin 13' having vertical dimension desired to be reduced. The bottom part 33 of the selected semiconductor fin 13' having the injection chemical species is subjected to selective etching for a semiconductor material where the injection chemical species does not exist, i.e., the semiconductor material at the upper part 23 of the semiconductor fin, and of other semiconductor fin 13 where the injection chemical species does not exist. Consequently, a FinFET having a complete vertical dimension and a high on current, and a FinFET having a reduced vertical dimension and a low on current are obtained on the same semiconductor substrate. Vertical dimension of a semiconductor fin in a selected FinFET can be adjusted, by adjusting the depth of the injection chemical species.

Abstract translation: 要解决的问题：提供包括具有不同垂直尺寸的翅片的三栅极FinFET和双栅极FinFET的半导体结构，并提供半导体结构的制造方法。解决方案：将含锗的注入化学物质注入到 所选择的半导体鳍片13'的底部33具有希望减小的垂直尺寸。 对具有注入化学物质的所选择的半导体鳍片13'的底部33进行对不存在注入化学物质的半导体材料（即，半导体鳍片的上部23处的半导体材料）的选择性蚀刻，以及 的其他半导体鳍片13，其中注入化学物质不存在。 因此，在相同的半导体衬底上获得具有完整的垂直尺寸和高导通电流的FinFET和具有减小的垂直尺寸和低导通电流的FinFET。 通过调整注入化学物质的深度，可以调整所选FinFET中半导体鳍片的垂直尺寸。

公开(公告)号：JP2008010871A

公开(公告)日：2008-01-17

申请号：JP2007165646

申请日：2007-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  LIN HONG

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L29/045 ,  H01L29/665 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/78618 ,  Y10S257/902

Abstract: PROBLEM TO BE SOLVED: To provide an improved metal-oxide-semiconductor field effect transistor (MOSFET) device with stress-inducing structures located at the source and drain (S/D) regions. SOLUTION: Each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有位于源极和漏极（S / D）区域的应力诱导结构的改进的金属氧化物半导体场效应晶体管（MOSFET）器件。 解决方案：每个MOSFET包括位于半导体衬底中的源区和漏区。 这种源极和漏极区域包括具有相对于半导体衬底的上表面倾斜的一个或多个侧壁表面的凹槽。 应力诱导电介质层位于源极和漏极区域的凹部的倾斜侧壁表面上。 这样的MOSFET可以容易地通过半导体衬底的晶体蚀刻形成，以形成具有倾斜侧壁表面的凹部，随后在其上沉积应力诱导介电层。 版权所有（C）2008，JPO＆INPIT