Abstract:
Dummy Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a bumper extending from a Micro-Electro-Mechanical System (MEMS) beam structure provided within a cavity structure. The method further includes forming a dummy landing structure on an opposing side of the cavity structure from the MEMS beam, which is laterally offset from the bumper when the MEMS beam is in a non-actuated state.
Abstract:
PROBLEM TO BE SOLVED: To provide a new dual damascene wiring structure that improves the efficiency of dual damascene wiring by improving a dual damascene wiring formation method. SOLUTION: This method concerns the formation of a dual damascene interconnection structure and a related structure. In this formation, the related structure includes a dual damascene wiring in a dielectric substance layer. The above dual damascene wiring is extended into the dielectric substance layer at a distance shorter than the thickness of the corresponding dielectric substance layer, and a dual damascene via bar is integrated with the bottom of the dual damascene wiring and is extended toward the bottom of the dielectric substance later from that bottom. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a more reliable damascene capacitor structure by preventing the occurrence of leakage and dielectric breakdown between capacitor plates. SOLUTION: A capacitor device is provided with a trench which is formed into an inter-level dielectric insulator layer and has sidewalls, a first thin lower conductor plate 32 formed on the bottom of the trench, and a second upper conductor plate 44 having a surface which is commonly formed as the surface of the dielectric insulator layer also. The capacitor device is also provided with a dielectric layer 42 formed between the conductor plates 32 and 44. The dielectric layer 42 prevents one of the conductor plates 32 and 44 from extending to the sidewalls of the trench and at least one upper corner of the conductor plate from extending toward the upper part of the trench.
Abstract:
A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.
Abstract:
An image sensor (20) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (135a, 135b) allowing for incorporation of a thinner interlevel dielectric stack (130a-130c) to result in a pixel array (100) exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal (132a, 132b) that traverses the optical path of each pixel in the sensor array or, that have portions (50) of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer (142) may be formed atop the Cu metallization by a self-aligned deposition.
Abstract:
PROBLEM TO BE SOLVED: To provide a bipolar transistor structure with enhanced performance by optimizing junction interface characteristics between an emitter and a base, and a manufacturing method therefor.SOLUTION: The bipolar transistor includes: (1) a collector region 15 located at least in-part within a semiconductor substrate; (2) a base region 16 contacting the collector region; and (3) an emitter region 24 contacting the base region. A damaged region 16A that includes an oxygen impurity and at least one impurity selected from a group consisting of a fluorine impurity and a carbon impurity is formed in a layer 16 that includes a base of an emitter aperture at an interface between the emitter region and the base region, thus the performance of the bipolar transistor being enhanced. The impurities may be introduced into the interface by plasma etch treatment or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material composing the base region.
Abstract:
PROBLEM TO BE SOLVED: To provide a resistor that has a heat sink with excellent heat conduction. SOLUTION: This heat sink includes a conduction path that has a high-thermal conductivity metal and other thermal conductors. In order that an electrical resistor may not be short-circuited to earth by this thermal resistor, a thin layer with a high-thermal conductivity electric insulator is interposed between the thermal conductor and the resistor's body. Accordingly, since heat is conducted to the heat sink in a direction in which the thermal conductor with high thermal conductivity moves away from the resistor, the resistor can pass a large amount of current. In addition to the fact that a parasitic capacitance and other electric parasitic actions that help reduce high-frequency responses from the electric resistor are lowered, various structures of a thermal conductor and heat sink are achieved through which favorable thermal conduction characteristics are obtained. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a metal capacitor installed on a chip. SOLUTION: Capacitors (60, 126) manufactured on a semiconductor chip have strap/contacts (41A, 119A), which mutually connect bottom plates (41B, 111A) of a capacitor to a chip circuit. In one version, an extension part of a material, constituting a bottom plate of a capacitor forms a strap contact. In the other version, a capacitor (185) comprises a folded bottom plate, which uses an available space and therefore increases its capacitance, a dielectric layer and a top plate. By means of a plurality of manufacturing methods, manufacturing of these capacitors of various versions can be incorporated in a standard dual or single-damascene manufacturing process, including a copper damascene process.
Abstract:
PROBLEM TO BE SOLVED: To facilitate mutual connection between a connecting wire and a mutual connection stud by using a sidewall spacer on the side face of the connecting wire for widening the contact area between the connecting wire and the connection stud. SOLUTION: A semiconductor part 100 has a connection stud 102 connecting the first connecting wire 104 to the second connecting wire 106. The first connecting wire 104 and the second connecting wire 106 and made of a metallic conductor in high conductivity. A substitute conductive path is formed between the first connecting wire 104 and the mutual connection stud 102 by a sidewall spacer 2 added to the first connecting wire 104 before an insulator is bonded. Especially, the side wall 22 comes into contact with a Ti/TiN layer 108 along the outer side thereof. Furthermore, the connection stud 102 is connected to the sidewall spacer 122 which is further connected to the first connecting wire 104. Accordingly, the sidewall spacer 122 is connected to the first connecting wire 104 along the whole sidewall thereof.