MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES
    21.
    发明申请
    MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES 审中-公开
    微电子机械系统(MEMS)结构和设计结构

    公开(公告)号:WO2014181202A2

    公开(公告)日:2014-11-13

    申请号:PCT/IB2014060145

    申请日:2014-03-25

    Applicant: IBM IBM CHINA LTD

    CPC classification number: B81B3/001

    Abstract: Dummy Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a bumper extending from a Micro-Electro-Mechanical System (MEMS) beam structure provided within a cavity structure. The method further includes forming a dummy landing structure on an opposing side of the cavity structure from the MEMS beam, which is laterally offset from the bumper when the MEMS beam is in a non-actuated state.

    Abstract translation: 公开了虚拟微机电系统(MEMS)结构,制造方法和设计结构。 该方法包括形成从设置在空腔结构内的微电子机械系统(MEMS)梁结构延伸的保险杠。 该方法还包括在空腔结构的与MEMS光束相对的一侧上形成虚拟着陆结构,当MEMS射束处于非致动状态时,其从该保险杠侧向偏移。

    Dual damascene wiring and its forming method
    22.
    发明专利
    Dual damascene wiring and its forming method 有权
    双面接线及其成型方法

    公开(公告)号:JP2006054433A

    公开(公告)日:2006-02-23

    申请号:JP2005183686

    申请日:2005-06-23

    Abstract: PROBLEM TO BE SOLVED: To provide a new dual damascene wiring structure that improves the efficiency of dual damascene wiring by improving a dual damascene wiring formation method. SOLUTION: This method concerns the formation of a dual damascene interconnection structure and a related structure. In this formation, the related structure includes a dual damascene wiring in a dielectric substance layer. The above dual damascene wiring is extended into the dielectric substance layer at a distance shorter than the thickness of the corresponding dielectric substance layer, and a dual damascene via bar is integrated with the bottom of the dual damascene wiring and is extended toward the bottom of the dielectric substance later from that bottom. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题:提供一种新的双镶嵌布线结构,通过改进双镶嵌布线形成方法来提高双镶嵌布线的效率。

    解决方案:该方法涉及形成双镶嵌互连结构和相关结构。 在该结构中,相关结构包括电介质层中的双镶嵌布线。 上述双镶嵌布线以比对应的电介质层的厚度短的距离延伸到电介质层中,并且双镶嵌通孔条与双镶嵌布线的底部一体化并且朝向底部延伸 电介质物质晚于该底部。 版权所有(C)2006,JPO&NCIPI

    CAPACITOR DEVICE AND METHOD OF FORMING CAPACITOR

    公开(公告)号:JP2002313939A

    公开(公告)日:2002-10-25

    申请号:JP2002060480

    申请日:2002-03-06

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a more reliable damascene capacitor structure by preventing the occurrence of leakage and dielectric breakdown between capacitor plates. SOLUTION: A capacitor device is provided with a trench which is formed into an inter-level dielectric insulator layer and has sidewalls, a first thin lower conductor plate 32 formed on the bottom of the trench, and a second upper conductor plate 44 having a surface which is commonly formed as the surface of the dielectric insulator layer also. The capacitor device is also provided with a dielectric layer 42 formed between the conductor plates 32 and 44. The dielectric layer 42 prevents one of the conductor plates 32 and 44 from extending to the sidewalls of the trench and at least one upper corner of the conductor plate from extending toward the upper part of the trench.

    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION
    25.
    发明申请
    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION 审中-公开
    通过光刻对齐和注册来实现硅通孔

    公开(公告)号:WO2011090852A2

    公开(公告)日:2011-07-28

    申请号:PCT/US2011020913

    申请日:2011-01-12

    Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

    Abstract translation: 制造集成电路结构的方法在衬底(100;图1)中形成第一开口并用保护性衬垫排列第一开口。 (102)该方法将材料沉积到第一开口(104)中并且在衬底上形成保护材料。 保护材料包括过程控制标记并且包括在第一开口上方并与第一开口对齐的第二开口。 (108)该方法通过保护材料中的第二开口从第一开口移除材料。 (110)过程控制标记包括保护材料内的凹部,其仅部分地延伸穿过保护材料,使得过程控制标记下方的部分基板不受移除材料的过程的影响。

    CMOS IMAGER OF ELIMINATING HIGH REFLECTIVITY INTERFACES
    26.
    发明申请
    CMOS IMAGER OF ELIMINATING HIGH REFLECTIVITY INTERFACES 审中-公开
    消除高反射性界面的CMOS图像

    公开(公告)号:WO2006071540A3

    公开(公告)日:2007-04-12

    申请号:PCT/US2005045328

    申请日:2005-12-14

    Abstract: An image sensor (20) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (135a, 135b) allowing for incorporation of a thinner interlevel dielectric stack (130a-130c) to result in a pixel array (100) exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal (132a, 132b) that traverses the optical path of each pixel in the sensor array or, that have portions (50) of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer (142) may be formed atop the Cu metallization by a self-aligned deposition.

    Abstract translation: 一种图像传感器(20)及其制造方法,其中传感器包括铜(Cu)金属化水平(135a,135b),允许结合更薄的层间电介质堆叠(130a-130c)以产生呈现增加的像素阵列(100) 光敏感。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属(132a,132b)的最小厚度的结构,或者具有从每个的光路中选择性地去除的阻挡层金属的部分(50) 像素,从而最小化反射率。 也就是说,通过实现各种块或单掩模方法,在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中,阻挡金属层(142)可以通过自对准沉积形成在Cu金属化之上。

    Bipolar transistor structure and manufacturing method therefor
    27.
    发明专利
    Bipolar transistor structure and manufacturing method therefor 有权
    双极晶体管结构及其制造方法

    公开(公告)号:JP2011003907A

    公开(公告)日:2011-01-06

    申请号:JP2010141326

    申请日:2010-06-22

    Abstract: PROBLEM TO BE SOLVED: To provide a bipolar transistor structure with enhanced performance by optimizing junction interface characteristics between an emitter and a base, and a manufacturing method therefor.SOLUTION: The bipolar transistor includes: (1) a collector region 15 located at least in-part within a semiconductor substrate; (2) a base region 16 contacting the collector region; and (3) an emitter region 24 contacting the base region. A damaged region 16A that includes an oxygen impurity and at least one impurity selected from a group consisting of a fluorine impurity and a carbon impurity is formed in a layer 16 that includes a base of an emitter aperture at an interface between the emitter region and the base region, thus the performance of the bipolar transistor being enhanced. The impurities may be introduced into the interface by plasma etch treatment or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material composing the base region.

    Abstract translation: 要解决的问题:通过优化发射极和基极之间的结界面特性来提供具有增强性能的双极晶体管结构及其制造方法。解决方案:双极晶体管包括:(1)至少位于 在半导体衬底内; (2)与收集器区域接触的基极区域16; 和(3)与基极区域接触的发射极区域24。 包含氧杂质和选自氟杂质和碳杂质的至少一种杂质的受损区域16A形成在层16中,该层16包括在发射极区域和发射极区域之间的界面处的发射极孔径的基极 从而提高了双极晶体管的性能。 杂质可以通过等离子体蚀刻处理或替代地进行后处理,然后进行无水氨和氟化氢处理,构成基区的基材。

    CAPACITOR STRUCTURE AND ITS MANUFACTURING METHOD

    公开(公告)号:JP2001313373A

    公开(公告)日:2001-11-09

    申请号:JP2001098235

    申请日:2001-03-30

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a metal capacitor installed on a chip. SOLUTION: Capacitors (60, 126) manufactured on a semiconductor chip have strap/contacts (41A, 119A), which mutually connect bottom plates (41B, 111A) of a capacitor to a chip circuit. In one version, an extension part of a material, constituting a bottom plate of a capacitor forms a strap contact. In the other version, a capacitor (185) comprises a folded bottom plate, which uses an available space and therefore increases its capacitance, a dielectric layer and a top plate. By means of a plurality of manufacturing methods, manufacturing of these capacitors of various versions can be incorporated in a standard dual or single-damascene manufacturing process, including a copper damascene process.

    MUTUAL CONNECTION USING METALLIC SPACER AND ITS MANUFACTURING METHOD

    公开(公告)号:JPH10289949A

    公开(公告)日:1998-10-27

    申请号:JP9198298

    申请日:1998-04-03

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To facilitate mutual connection between a connecting wire and a mutual connection stud by using a sidewall spacer on the side face of the connecting wire for widening the contact area between the connecting wire and the connection stud. SOLUTION: A semiconductor part 100 has a connection stud 102 connecting the first connecting wire 104 to the second connecting wire 106. The first connecting wire 104 and the second connecting wire 106 and made of a metallic conductor in high conductivity. A substitute conductive path is formed between the first connecting wire 104 and the mutual connection stud 102 by a sidewall spacer 2 added to the first connecting wire 104 before an insulator is bonded. Especially, the side wall 22 comes into contact with a Ti/TiN layer 108 along the outer side thereof. Furthermore, the connection stud 102 is connected to the sidewall spacer 122 which is further connected to the first connecting wire 104. Accordingly, the sidewall spacer 122 is connected to the first connecting wire 104 along the whole sidewall thereof.

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