公开(公告)号：WO2014181202A2

公开(公告)日：2014-11-13

申请号：PCT/IB2014060145

申请日：2014-03-25

Applicant: IBM ,  IBM CHINA LTD

Inventor： STAMPER ANTHONY K

CPC classification number: B81B3/001

Abstract: Dummy Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a bumper extending from a Micro-Electro-Mechanical System (MEMS) beam structure provided within a cavity structure. The method further includes forming a dummy landing structure on an opposing side of the cavity structure from the MEMS beam, which is laterally offset from the bumper when the MEMS beam is in a non-actuated state.

Abstract translation: 公开了虚拟微机电系统（MEMS）结构，制造方法和设计结构。 该方法包括形成从设置在空腔结构内的微电子机械系统（MEMS）梁结构延伸的保险杠。 该方法还包括在空腔结构的与MEMS光束相对的一侧上形成虚拟着陆结构，当MEMS射束处于非致动状态时，其从该保险杠侧向偏移。

公开(公告)号：JP2006054433A

公开(公告)日：2006-02-23

申请号：JP2005183686

申请日：2005-06-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MCDEVITT THOMAS L ,  STAMPER ANTHONY K

IPC: H01L21/768 ,  H01L21/822 ,  H01L27/04

CPC classification number: H01L21/76838 ,  H01L21/76802 ,  H01L21/76808 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a new dual damascene wiring structure that improves the efficiency of dual damascene wiring by improving a dual damascene wiring formation method. SOLUTION: This method concerns the formation of a dual damascene interconnection structure and a related structure. In this formation, the related structure includes a dual damascene wiring in a dielectric substance layer. The above dual damascene wiring is extended into the dielectric substance layer at a distance shorter than the thickness of the corresponding dielectric substance layer, and a dual damascene via bar is integrated with the bottom of the dual damascene wiring and is extended toward the bottom of the dielectric substance later from that bottom. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种新的双镶嵌布线结构，通过改进双镶嵌布线形成方法来提高双镶嵌布线的效率。

解决方案：该方法涉及形成双镶嵌互连结构和相关结构。 在该结构中，相关结构包括电介质层中的双镶嵌布线。 上述双镶嵌布线以比对应的电介质层的厚度短的距离延伸到电介质层中，并且双镶嵌通孔条与双镶嵌布线的底部一体化并且朝向底部延伸 电介质物质晚于该底部。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005217420A

公开(公告)日：2005-08-11

申请号：JP2005021358

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  COLBURN MATTHEW E ,  COONEY EDWARD C III ,  DALTON TIMOTHY J ,  FITZSIMMONS JOHN A ,  GAMBINO JEFFREY P ,  HUANG ELBERT E ,  LANE MICHAEL W ,  MCGAHAY VINCENT J ,  NICHOLSON LEE M ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SANKARAN SUJATHA ,  SHAW THOMAS M ,  SIMON ANDREW H ,  STAMPER ANTHONY K

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种降低有效介电常数k eff 的高强度半导体器件，将互连中的级间垂直容量保持在低水平，并且制造方法 一样的。 解决方案：制造该器件的方法包括提供具有至少一个互连130的绝缘层120和在绝缘层上形成亚光刻模板掩模150的步骤的结构的步骤。 通过使用选择性蚀刻步骤，通过通过亚光刻模板掩模对绝缘层进行蚀刻，在至少一个相互连接附近形成亚光刻部件135a。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2002313939A

公开(公告)日：2002-10-25

申请号：JP2002060480

申请日：2002-03-06

Applicant: IBM

Inventor： STAMPER ANTHONY K

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/334 ,  H01L21/768 ,  H01L21/822 ,  H01L27/08

Abstract: PROBLEM TO BE SOLVED: To provide a more reliable damascene capacitor structure by preventing the occurrence of leakage and dielectric breakdown between capacitor plates. SOLUTION: A capacitor device is provided with a trench which is formed into an inter-level dielectric insulator layer and has sidewalls, a first thin lower conductor plate 32 formed on the bottom of the trench, and a second upper conductor plate 44 having a surface which is commonly formed as the surface of the dielectric insulator layer also. The capacitor device is also provided with a dielectric layer 42 formed between the conductor plates 32 and 44. The dielectric layer 42 prevents one of the conductor plates 32 and 44 from extending to the sidewalls of the trench and at least one upper corner of the conductor plate from extending toward the upper part of the trench.

公开(公告)号：WO2011090852A2

公开(公告)日：2011-07-28

申请号：PCT/US2011020913

申请日：2011-01-12

Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

Abstract translation: 制造集成电路结构的方法在衬底（100;图1）中形成第一开口并用保护性衬垫排列第一开口。 （102）该方法将材料沉积到第一开口（104）中并且在衬底上形成保护材料。 保护材料包括过程控制标记并且包括在第一开口上方并与第一开口对齐的第二开口。 （108）该方法通过保护材料中的第二开口从第一开口移除材料。 （110）过程控制标记包括保护材料内的凹部，其仅部分地延伸穿过保护材料，使得过程控制标记下方的部分基板不受移除材料的过程的影响。

公开(公告)号：WO2006071540A3

公开(公告)日：2007-04-12

申请号：PCT/US2005045328

申请日：2005-12-14

Applicant: IBM ,  ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

IPC: H01L29/04

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

Abstract: An image sensor (20) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (135a, 135b) allowing for incorporation of a thinner interlevel dielectric stack (130a-130c) to result in a pixel array (100) exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal (132a, 132b) that traverses the optical path of each pixel in the sensor array or, that have portions (50) of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer (142) may be formed atop the Cu metallization by a self-aligned deposition.

Abstract translation: 一种图像传感器（20）及其制造方法，其中传感器包括铜（Cu）金属化水平（135a，135b），允许结合更薄的层间电介质堆叠（130a-130c）以产生呈现增加的像素阵列（100） 光敏感。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属（132a，132b）的最小厚度的结构，或者具有从每个的光路中选择性地去除的阻挡层金属的部分（50） 像素，从而最小化反射率。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层（142）可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：JP2011003907A

公开(公告)日：2011-01-06

申请号：JP2010141326

申请日：2010-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： STAMPER ANTHONY K ,  DAHLSTROM MATTIAS ERIK ,  BENOIT JOHN JOSEPH ,  GRAY PETER BRIAN ,  DUPUIS MARK DAVID

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L29/34 ,  H01L29/66272

Abstract: PROBLEM TO BE SOLVED: To provide a bipolar transistor structure with enhanced performance by optimizing junction interface characteristics between an emitter and a base, and a manufacturing method therefor.SOLUTION: The bipolar transistor includes: (1) a collector region 15 located at least in-part within a semiconductor substrate; (2) a base region 16 contacting the collector region; and (3) an emitter region 24 contacting the base region. A damaged region 16A that includes an oxygen impurity and at least one impurity selected from a group consisting of a fluorine impurity and a carbon impurity is formed in a layer 16 that includes a base of an emitter aperture at an interface between the emitter region and the base region, thus the performance of the bipolar transistor being enhanced. The impurities may be introduced into the interface by plasma etch treatment or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material composing the base region.

Abstract translation: 要解决的问题：通过优化发射极和基极之间的结界面特性来提供具有增强性能的双极晶体管结构及其制造方法。解决方案：双极晶体管包括：（1）至少位于 在半导体衬底内; （2）与收集器区域接触的基极区域16; 和（3）与基极区域接触的发射极区域24。 包含氧杂质和选自氟杂质和碳杂质的至少一种杂质的受损区域16A形成在层16中，该层16包括在发射极区域和发射极区域之间的界面处的发射极孔径的基极 从而提高了双极晶体管的性能。 杂质可以通过等离子体蚀刻处理或替代地进行后处理，然后进行无水氨和氟化氢处理，构成基区的基材。

公开(公告)号：JP2006196894A

公开(公告)日：2006-07-27

申请号：JP2006001619

申请日：2006-01-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HOOK TERENCE B ,  RASSEL ROBERT M ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  MURPHY WILLIAM J

IPC: H01L23/36 ,  H01L23/373

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a resistor that has a heat sink with excellent heat conduction. SOLUTION: This heat sink includes a conduction path that has a high-thermal conductivity metal and other thermal conductors. In order that an electrical resistor may not be short-circuited to earth by this thermal resistor, a thin layer with a high-thermal conductivity electric insulator is interposed between the thermal conductor and the resistor's body. Accordingly, since heat is conducted to the heat sink in a direction in which the thermal conductor with high thermal conductivity moves away from the resistor, the resistor can pass a large amount of current. In addition to the fact that a parasitic capacitance and other electric parasitic actions that help reduce high-frequency responses from the electric resistor are lowered, various structures of a thermal conductor and heat sink are achieved through which favorable thermal conduction characteristics are obtained. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有散热器的具有优异热传导性的电阻器。 解决方案：该散热器包括具有高导热性金属和其他热导体的导电路径。 为了使该电阻器不会被该热电阻器短路到地，具有高导热电绝缘体的薄层插入在热导体和电阻体之间。 因此，由于在热导率高的导体从电阻器移开的方向向散热器传导热量，所以电阻器能够通过大量的电流。 除了有助于降低来自电阻器的高频响应的寄生电容和其他电寄生作用降低之外，还实现了热导体和散热器的各种结构，从而获得了良好的热传导特性。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2001313373A

公开(公告)日：2001-11-09

申请号：JP2001098235

申请日：2001-03-30

Applicant: IBM

Inventor： KERRY BERNSTEIN ,  GEFFKEN ROBERT M ,  STAMPER ANTHONY K ,  STEVEN A SAINT ONGE

IPC: H01L23/52 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a metal capacitor installed on a chip. SOLUTION: Capacitors (60, 126) manufactured on a semiconductor chip have strap/contacts (41A, 119A), which mutually connect bottom plates (41B, 111A) of a capacitor to a chip circuit. In one version, an extension part of a material, constituting a bottom plate of a capacitor forms a strap contact. In the other version, a capacitor (185) comprises a folded bottom plate, which uses an available space and therefore increases its capacitance, a dielectric layer and a top plate. By means of a plurality of manufacturing methods, manufacturing of these capacitors of various versions can be incorporated in a standard dual or single-damascene manufacturing process, including a copper damascene process.

公开(公告)号：JPH10289949A

公开(公告)日：1998-10-27

申请号：JP9198298

申请日：1998-04-03

Applicant: IBM

Inventor： CRONIN JOHN E ,  HARTSWICK THOMAS J ,  STAMPER ANTHONY K

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To facilitate mutual connection between a connecting wire and a mutual connection stud by using a sidewall spacer on the side face of the connecting wire for widening the contact area between the connecting wire and the connection stud. SOLUTION: A semiconductor part 100 has a connection stud 102 connecting the first connecting wire 104 to the second connecting wire 106. The first connecting wire 104 and the second connecting wire 106 and made of a metallic conductor in high conductivity. A substitute conductive path is formed between the first connecting wire 104 and the mutual connection stud 102 by a sidewall spacer 2 added to the first connecting wire 104 before an insulator is bonded. Especially, the side wall 22 comes into contact with a Ti/TiN layer 108 along the outer side thereof. Furthermore, the connection stud 102 is connected to the sidewall spacer 122 which is further connected to the first connecting wire 104. Accordingly, the sidewall spacer 122 is connected to the first connecting wire 104 along the whole sidewall thereof.