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    26.
    发明专利
    未知

    公开(公告)号：DE102004014448B4

    公开(公告)日：2007-06-14

    申请号：DE102004014448

    申请日：2004-03-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER

    IPC: H04B3/04 ,  H03K5/13 ,  H03K5/159 ,  H03L7/081 ,  H04B1/10 ,  H04B10/18 ,  H04L7/033 ,  H04M1/58 ,  H04M1/74

    Abstract: The device has a master delay locked loop (MDLL) for producing equidistant reference phase signals, a slave delay locked loop (SDLL) with serial connected slave delay units , each with a slave delay element, and an analog amplifier that amplifies the delayed element output signal by a weighting coefficient to generate a weighted delay signal and a subtraction device for subtracting the weighted delayed signal selected by a multiplexer from the received data signal to generate a distortion corrected output data signal. An independent claim is also included for the following: (a) a method of distortion correction of a received data signal.

    27.
    发明专利
    未知

    公开(公告)号：DE102005040109A1

    公开(公告)日：2007-03-15

    申请号：DE102005040109

    申请日：2005-08-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WALLNER PAUL ,  SCHAEFER ANDRE ,  GREGORIUS PETER

    IPC: G11C7/10

    Abstract: A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.

    29.
    发明专利
    未知

    公开(公告)号：DE10207315B4

    公开(公告)日：2007-01-04

    申请号：DE10207315

    申请日：2002-02-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ENGL BERNHARD ,  GREGORIUS PETER

    IPC: H04L25/04 ,  H03L7/089 ,  H03L7/091 ,  H04L7/033

    Abstract: A CDR circuit arrangement, for example for a transceiver module, features a data recovery unit ( 4 ) for the recovery of the data contained in a received signal (DATA) by scanning this received data signal, and a phase evaluation unit for the determination of a suitable phase position for the scanning carried out by the data recovery unit ( 4 ). The phase evaluation unit comprises a scanning device ( 1 ) for the oversampling of a the received data signal (DATA) in accordance with several different scanning phases (P 0 -P 6 ), a phase detector device ( 2 ) for the evaluation of the scanning values (A 0 -A 6 ) accordingly prepared by the scanning device ( 1 ), in order thereby to derive intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ), which classify the phase error during the scanning of the data signal by the scanning device ( 1 ) in respect of its size and direction of deviation, as well as a filter device ( 3 ), in order to subject the intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ) generated by the phase detector device ( 2 ) to a weighted filtering process. In this situation, a setting signal (DeltaP) is generated by the filter device ( 3 ) for the subsequent regulation and control of the scanning phases (P 0 -P 6 ) of the scanning device ( 1 ).

    30.
    发明专利
    未知

    公开(公告)号：DE10137150B4

    公开(公告)日：2007-01-04

    申请号：DE10137150

    申请日：2001-07-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GREGORIUS PETER ,  HANNEBERG ARMIN ,  LAASER PETER

    IPC: H03F3/45 ,  H04L25/02 ,  H04L25/20

    Abstract: A line driver ( 3 ) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors ( 14, 15 ) for generating transmission impulses as a function of the data to be transmitted, whereby the transmission impulses are preferably output via cascode transistors ( 16, 17 ), each with the differential pair transistors ( 14, 15 ) forming a cascode circuit, onto the data transmission line ( 8, 9 ) connected to the line driver ( 3 ). For reproducing the behaviour of the differential pair a replica differential pair with replica differential pair transistors ( 18, 19 ) is provided, generating replica impulses corresponding to the transmission impulses, which replica impulses can be fed via replica cascode transistors ( 20, 21 ) to a hybrid integrated circuit ( 6 ) for effecting echo compensation in relation to impulses received via the data transmission line ( 8, 9 )

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