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公开(公告)号：DE102005055652A1
公开(公告)日：2006-07-20
申请号：DE102005055652
申请日：2005-11-22
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HAPP THOMAS
IPC: G11C13/00
Abstract: A memory cell device and method that includes a memory cell, and first and second write pulse signals. The memory cell has phase-change material capable of being set and capable of being reset. The first and second write pulse signals are used for a single reset operation of the memory cell. The first write pulse signal heats and melts a first portion of the phase-change material of the memory cell. The second write pulse signal heats and melts a second portion of the phase-change material of the memory cell.
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公开(公告)号：DE102004056973A1
公开(公告)日：2006-06-01
申请号：DE102004056973
申请日：2004-11-25
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HAPP THOMAS , SYMANCZYK RALF
IPC: H01L27/24
Abstract: Method for producing and integrating solid body electrolyte memory cells comprises depositing a lower electrode material (7) on a silicon substrate (6), structuring the lower electrode material to form lower electrode strips, producing a layer stack on the electrode strips by depositing layers of a solid electrolyte material (4), a reactive material (9) and an upper electrode material (10), structuring the upper electrode material perpendicular to the electrode strips by etching the upper electrode material to produce upper electrode strips and structuring the remaining layer stack perpendicular to the lower electrode strips by etching the active layers, solid electrolyte material and reactive material to produce trenches (13) in the layer stack. An independent claim is also included for a system comprising a memory element with a solid electrolyte memory cell.
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公开(公告)号：DE102004026003B3
公开(公告)日：2006-01-19
申请号：DE102004026003
申请日：2004-05-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HAPP THOMAS
Abstract: A memory cell arrangement includes a set of word lines and bit lines and at least one chain of series-connected memory elements which is electrically connected to one of the bit lines. The memory elements each include a resistive memory cell, which can be switched between a low-resistance ON state and a high-resistance OFF state, and a transistor which is electrically connected to the resistive memory cell in a parallel circuit. The ON resistance of the transistor, which has been turned on, of a memory element is smaller than the ON resistance of the memory cell which has been switched to its low-resistance ON state. Each transistor in a respective chain is electrically connected to one of the word lines.
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公开(公告)号：DE102004026111A1
公开(公告)日：2005-12-22
申请号：DE102004026111
申请日：2004-05-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HAPP THOMAS , PINNOW CAY-UWE
IPC: G11C13/00 , H01L21/8239 , H01L27/24 , H01L45/00
Abstract: The method involves production of a solid electrolyte memory cell which has a memory section. The cell has a solid electrolyte material area (11) made up of a solid electrolyte material (11'). The area is activated by doping it with a dopant (12) and then the cell is irradiated with ions or ion beam (30) either partly or completely.
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公开(公告)号：DE102004022618A1
公开(公告)日：2005-12-15
申请号：DE102004022618
申请日：2004-05-07
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SYMANCZYK RALF , HAPP THOMAS
IPC: B82B3/00 , H01L21/8247
Abstract: The method involves disposing in a substrate a channel region (3), in which a charge carrier channel can be formed. A first insulation layer is provided on the channel region. A nano-porous mask layer is applied which comprises pore openings. A memory material is inserted into the pore openings. The mask layer is selectively removed so that the memory material remains as nano-point-like memory regions on the insulating layer. A second insulating layer is applied on the first insulating layer and between the memory regions, so that the memory regions are completely insulated from each other.
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Patent Agency Ranking
公开(公告)号：DE102005018344A1
公开(公告)日：2005-12-01
申请号：DE102005018344
申请日：2005-04-20
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ROEHR THOMAS , HAPP THOMAS
IPC: G02F1/153 , G11C13/02 , G11C16/00 , H01L23/525 , H01L27/24 , H01L29/02 , H01L45/00 , H01L47/00 , H03F3/45
Abstract: A switching device to be reversibly switched between an electrically isolating off-state and an electrically conducting on-state for use in, e.g., a reconfigurable interconnect. The device includes two separate electrodes, one of which being a reactive metal electrode and the other one being an inert electrode, and a solid state electrolyte arranged between the electrodes and being capable of electrically isolating the electrodes to define the off-state. The reactive metal electrode and the solid state electrolyte also being capable of forming a redox-system having a minimum voltage (turn-on voltage) to start a redox-reaction, which results in generating metal ions that are released into the solid state electrolyte. The metal ions are reduced to increase a metal concentration within the solid state electrolyte, wherein an increase of the metal concentration results in a conductive metallic connection bridging the electrodes to define the on-state.
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公开(公告)号：DE102008025473B4
公开(公告)日：2015-10-15
申请号：DE102008025473
申请日：2008-05-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HAPP THOMAS , KASKO IGOR , WALTER ANDREAS
Abstract: Verfahren zum Herstellen einer integrierten Schaltung mit einer Mehrzahl von Widerstandsänderungsspeicherzellen, wobei das Verfahren aufweist: – Ausbilden eines Halbleitersubstrats; – Ausbilden einer Isolationsschicht auf dem Halbleitersubstrat; – Ausbilden eines Grabens innerhalb der Isolationsschicht; – Einführen von Dotiermaterial eines ersten Leitungstyps durch den Graben in das Halbleitersubstrat, wodurch ein erstes Halbleitergebiet gebildet wird; – Füllen des Grabens mit einem Füllmaterial; – Ausbilden eines Kontaktloches innerhalb der Isolationsschicht benachbart zu dem Graben; – Einführen von Dotiermaterial eines zweiten Leitungstyps durch das Kontaktloch in das Halbleitersubstrat, wodurch ein zweites Halbleitergebiet gebildet wird, das zusammen mit dem ersten Halbleitergebiet eine Diode mit einem pn-Übergang ausbildet, wobei der pn-Übergang ein laterales pn-Übergangsgebiet bildet; – Entfernen des Füllmaterials; – Füllen des Grabens und des Kontaktloches mit leitendem Material, wodurch in dem Graben eine Wortleitung auf dem Halbleitersubstrat, und in dem Kontaktloch ein leitendes Verbindungselement gebildet wird; – Ausbilden eines Speicherelementes oberhalb des Halbleitersubstrats derart, dass das Speicherelement über das leitende Verbindungselement mit dem zweiten Halbleitergebiet verbunden ist.
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公开(公告)号：DE102008028934A1
公开(公告)日：2009-01-02
申请号：DE102008028934
申请日：2008-06-18
Applicant: INFINEON TECHNOLOGIES AG , QIMONDA AG
Inventor： PHILIPP JAN BORIS , NIRSCHL THOMAS , HAPP THOMAS
Abstract: An integrated circuit includes a diode including a first polarity region and a second polarity region. The second polarity region contacts a bottom and sidewalls of the first polarity region. The integrated circuit includes a first electrode coupled to the diode, a second electrode, and resistivity changing material between the first electrode and the second electrode.
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公开(公告)号：DE102004053602B4
公开(公告)日：2007-02-22
申请号：DE102004053602
申请日：2004-11-05
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HAPP THOMAS , KUND MICHAEL , SYMANCZYK RALF
Abstract: According to the invention, a memory system, and a process for controlling a memory component, to achieve different kinds of memory characteristics on one and the same memory component, is provided, the process comprising the steps: Sending out a signal to select one of several possible modes for the memory component; and Operating the memory component in accordance with the specific mode selected by the signal.
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公开(公告)号：DE102004041893B4
公开(公告)日：2006-11-23
申请号：DE102004041893
申请日：2004-08-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SYMANCZYK RALF , PINNOW CAY-UWE , HAPP THOMAS
IPC: H01L21/822 , H01L27/24
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