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    23.
    发明专利
    未知

    公开(公告)号：DE10158563C1

    公开(公告)日：2003-07-17

    申请号：DE10158563

    申请日：2001-11-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MEYER THORSTEN ,  FRANKOWSKY GERD ,  HEDLER HARRY ,  IRSIGLER ROLAND ,  VASQUEZ BARBARA

    IPC: H01L21/00 ,  H01L21/66 ,  H01L21/68 ,  H01L23/31 ,  H01L21/58

    Abstract: A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the following steps: arranging separated components on a surface-adhesive film at a predefined contact-specific spacing from one another, embedding the components in a flexible material in order to form a flexible holding frame which holds the components, pulling off the film, producing contact-making elements on the exposed side of the components, performing a functional test of the components and, if necessary, repair and/or replacement of components, and fixing and making contact with the components held in the holding frame on the module carrier.

    24.
    发明专利
    未知

    公开(公告)号：DE10157280A1

    公开(公告)日：2003-06-12

    申请号：DE10157280

    申请日：2001-11-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MEYER THORSTEN ,  FRANKOWSKY GERD ,  HEDLER HARRY ,  IRSIGLER ROLAND ,  VASQUEZ BARBARA

    IPC: H01L21/00 ,  H01L21/60 ,  H01L21/78 ,  H01L21/56

    Abstract: The invention creates a method for connection of circuit units (101a-10n) which are arranged on a wafer (100), in which the wafer (100) is fitted to a first film (102a), the wafer (100) is sawn such that the circuit units (101a-101n) which are arranged on the wafer (100) are separated, the functional circuit units (101d) are picked up by means of a handling device (101) and are placed down on a second film (102b) by means of the handling device (103), so as to produce a separation distance which can be predetermined between connection contacts of the circuit units (101d).

    25.
    发明专利
    未知

    公开(公告)号：DE10123686C1

    公开(公告)日：2003-03-20

    申请号：DE10123686

    申请日：2001-05-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HEDLER HARRY ,  IRSIGLER ROLAND ,  VASQUEZ BARBARA

    IPC: H01L21/66 ,  H01L23/525 ,  H01L21/768

    Abstract: A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least partially covering the circuit. The component comprises a rewiring of the contact pads. The inventive method comprises the following steps: each laser via is closed by means of a separate covering layer which is to be applied locally; a rewiring extending between the local covering layers is created; the local covering layers are removed; and the laser-induced correction is carried out by means of the open laser vias.

    27.
    发明专利
    未知

    公开(公告)号：DE102004041888B4

    公开(公告)日：2007-03-08

    申请号：DE102004041888

    申请日：2004-08-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HEDLER HARRY ,  MEYER THORSTEN ,  IRSIGLER ROLAND

    IPC: H01L23/50 ,  H01L21/60

    Abstract: The present invention provides an apparatus having stacked semiconductor components. Two semiconductor components (21, 26) are arranged such that their contact regions (28, 22) are opposite one another. A contact-connection device (29) forms a short electrical connection between the two contact regions (28, 22). The contact regions (28, 22) are connected to external contact regions (36) of the apparatus via a rewiring (23).

    28.
    发明专利
    未知

    公开(公告)号：DE102004041889A1

    公开(公告)日：2006-03-02

    申请号：DE102004041889

    申请日：2004-08-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： IRSIGLER ROLAND ,  HEDLER HARRY

    IPC: H01L21/60 ,  H01L23/50

    Abstract: A semiconductor device comprises at least one first semiconductor component being located in a first plane and comprising an active area which has a first contact region and at least one second semiconductor component being located in a second plane and comprising a second active area which has a second contact region. The second semiconductor component is located at a distance vertically to the first semiconductor component and is orientated relative to the first semiconductor component, so that the first active area faces away from the second semiconductor component and the second active area faces away from the first semiconductor component. An adhesive layer is arranged between the first and the second semiconductor components and a frame region adjoins laterally the first semiconductor component and the second semiconductor component on at least one side. The frame region comprises a first surface and a second surface which is located opposite to the second surface. A wiring device is introduced in the frame region and connects the first contact region to the second contact region.

    29.
    发明专利
    未知

    公开(公告)号：DE10221646B4

    公开(公告)日：2004-08-26

    申请号：DE10221646

    申请日：2002-05-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： POHL JENS ,  HEDLER HARRY ,  IRSIGLER ROLAND

    IPC: H01L23/48 ,  H01L21/98 ,  H01L23/31 ,  H01L23/485 ,  H01L25/065 ,  H01L23/50 ,  H01L21/60

    Abstract: Process for connecting chips comprises preparing first chip (1) with first main surface (HF1), preparing second chip (1') with second main surface (HF2) and third main surface (HF3), applying spacer (4) on chips to secure predetermined distance (h) between chips, applying adhesive (8) on first or second main surface, aligning first chip on second chip and joining chips, and hardening adhesive to form solid connection. An Independent claim is also included for a composite chip arrangement prepared by the above process.

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