公开(公告)号：DE102004027489A1

公开(公告)日：2005-12-29

申请号：DE102004027489

申请日：2004-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KERBER MARTIN

IPC: H01L21/66 ,  H01L21/00 ,  H01L21/58 ,  H01L21/78 ,  H01L23/544 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

Abstract: The invention relates to a method for arranging chips of a first substrate on a second substrate, in which the chips are grouped at least into first chips and into second chips, the first chips of the first substrate are singulated and the singulated first chips are arranged on the second substrate in such a way that each of the first chips on the second substrate is unambiguously assigned to the associated first chip on the first substrate.

公开(公告)号：DE59711121D1

公开(公告)日：2004-01-29

申请号：DE59711121

申请日：1997-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOM FELDE ANDREAS ,  BERTAGNOLLI EMMERICH ,  KERBER MARTIN

IPC: G01N27/414 ,  G01N27/327 ,  G01N27/416 ,  G01N33/487 ,  G06N3/00 ,  H01L29/78

Abstract: An MOS transistor has a gate electrode is electrically conductively connected to an exposed contact area (pad). The contact area is electrochemically corrosion-resistant and is dimensioned for connection to a living cell. The surface topology is relatively flat and the surface, with the exception of the contact area, is protected with a dielectric passivation layer.

公开(公告)号：DE19611692C2

公开(公告)日：2002-07-18

申请号：DE19611692

申请日：1996-03-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KERBER MARTIN ,  LACHNER RUDOLF

IPC: H01L21/266 ,  H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L29/73

公开(公告)号：DE59802919D1

公开(公告)日：2002-03-14

申请号：DE59802919

申请日：1998-09-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KERBER MARTIN ,  SCHMECKEBIER OLAF ,  KESSLER ELKE ,  FALTERMEIER JOSEF

IPC: G06F12/16 ,  G06F9/45 ,  G11C16/02 ,  G11C16/06 ,  G11C16/34

Abstract: When non volatile and electrically reprogrammable semiconductor memories are used as programm memories in computers and that, when so doing, one of the method step is constantly repeated in loop, said step is supplemented by at least one step of the same kind in that very loop procedure to increase data security. The steps comprised in one loop procedure involve a plurality of memory cells, resulting in a reduced load for each of them.

公开(公告)号：DE59608080D1

公开(公告)日：2001-12-06

申请号：DE59608080

申请日：1996-07-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHWALKE UDO ,  KERBER MARTIN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

Abstract: PCT No. PCT/DE96/01202 Sec. 371 Date Jan. 9, 1998 Sec. 102(e) Date Jan. 9, 1998 PCT Filed Jul. 4, 1996 PCT Pub. No. WO97/03462 PCT Pub. Date Jan. 30, 1997In the production of a dual work function CMOS circuit, a polysilicon layer is produced for the purpose of forming a gate structure, the average grain diameter of which polysilicon layer is greater than the minimum extent in the gate structure, in order to suppress lateral dopant diffusion. In particular, a constriction having a width less than the average grain diameter is produced in the gate structure.

公开(公告)号：DE10021095A1

公开(公告)日：2001-10-31

申请号：DE10021095

申请日：2000-04-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KERBER MARTIN ,  WURZER HELMUT ,  POMPL THOMAS

IPC: H01L21/265 ,  H01L21/316 ,  H01L21/314

Abstract: The method involves implanting ions (5) in a surface layer (4) of the semiconductor substrate (2) to form a first dielectric layer (7). A thermal oxidation process is performed to form a second dielectric layer (8) on the first dielectric layer (7). The semiconductor substrate is preferably a silicon substrate. The implanted ions are nitrogen ions (5). Prior to forming the dielectric, a cleaning process may be performed to clean the semiconductor substrate surface.