公开(公告)号：DE10353387A1

公开(公告)日：2005-06-30

申请号：DE10353387

申请日：2003-11-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOTEK MANFRED ,  HAEBERLEN OLIVER ,  POELZL MARTIN ,  RIEGER WALTER

IPC: H01L21/336 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

Abstract: In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement ( 1 ) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array ( 3 ) with cell array trenches ( 5 ) each containing a field electrode structure ( 11 ) and a gate electrode structure ( 10 ). The field electrode structure ( 11 ) is electrically conductively connected to the source metallization ( 15 ) by a connection trench ( 6 ) in the cell array ( 3 ).

公开(公告)号：DE102014116834B4

公开(公告)日：2021-01-21

申请号：DE102014116834

申请日：2014-11-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUMGARTL JOHANNES ,  ENGELHARDT MANFRED ,  KOTEK MANFRED ,  SCHULZE HANS-JOACHIM

IPC: H01L21/762 ,  H01L21/301 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

Abstract: Halbleitereinzelchip (1), der Folgendes aufweist:eine selektive Epitaxieschicht (60), die Vorrichtungsgebiete (100) aufweist; undeine Maskierungsstruktur (50), die um Seitenwände der Epitaxieschicht (60) derart angeordnet ist, dass sie eine Ringstruktur um die selektive Epitaxieschicht (60) herum bildet, wobei die Maskierungsstruktur (50) ein Gebiet der lokalen Oxidation von Silicium ist und wobei die Maskierungsstruktur (50) Teil von Chip-Vereinzelung-Schnittfugengebieten ist und diese definiert.

公开(公告)号：DE10354421A1

公开(公告)日：2005-06-30

申请号：DE10354421

申请日：2003-11-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOTEK MANFRED ,  RIEGER WALTER ,  HAEBERLEN OLIVER

IPC: H01L21/336 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78

Abstract: A process for producing a gate contact structure during the production of a trench high power transistor, comprises preparing a semiconductor substrate, forming a trench in the substrate, precipitating a gate dielectric (1) onto the inner walls of the trench, and precipitating a field oxide. The gate oxide is precipitated followed by a gate material (3). The gate material is then polyrecess etched. The liner (4) is then precipitated, and the liner and the intermediate oxide (5) are selectively etched. The liner consists of silicon nitride or oxynitride.

公开(公告)号：DE10164305A1

公开(公告)日：2003-07-10

申请号：DE10164305

申请日：2001-12-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RIEGER WALTER ,  KOTEK MANFRED

IPC: H01L21/336 ,  H01L29/06

Abstract: Production of an integrated DMOS transistor arrangement comprises using a mask region (M) having minimally extending contact holes (K) which correspond to the minimal structural size of the structuring technique, forming body reinforcing regions (BV), isotropically back etching the mask region, extending the contact holes, and contacting with conducting material by filling the holes. Preferred Features: The contact holes are filled to form a contact of a body region and a source region of a transistor device. The contact holes are formed using electromagnetic radiation and/or particle radiation.