公开(公告)号：DE10131276A1

公开(公告)日：2003-01-16

申请号：DE10131276

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  RICHTER FRANK ,  POPP MARTIN ,  WICH-GLASEN ANDREAS

IPC: H01L29/423 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

Abstract: The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow ION can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current IOFF. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.

公开(公告)号：DE19957123A1

公开(公告)日：2001-06-07

申请号：DE19957123

申请日：1999-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BENZINGER HERBERT ,  RICHTER FRANK

IPC: H01L27/108 ,  H01L21/8242

Abstract: The invention relates to a DRAM cell arrangement in which each memory cell (1) has a memory capacitor (2) and a read-out transistor (3). A buried strap contact (11) for connecting to the read-out transistor is produced by diffusing dopants out of the electrode of the memory capacitor (2). Said buried strap contact (11) is superposed by the implantations (12) of the source/drain area (5) of the read-out transistor (3), said implantation (12) of the source/drain area (5) forming the boundary of the space charge region of a p/n transition of the memory cell (1).