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    DRAM CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME
    1.
    发明申请
    DRAM CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME 审中-公开
    DRAM ZELLA ORDER及其制备方法

    公开(公告)号：WO0139248A2

    公开(公告)日：2001-05-31

    申请号：PCT/DE0003987

    申请日：2000-11-14

    Applicant: INFINEON TECHNOLOGIES AG ,  BENZINGER HERBERT ,  RICHTER FRANK

    Inventor： BENZINGER HERBERT ,  RICHTER FRANK

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L

    CPC classification number: H01L27/10867

    Abstract: The invention relates to a DRAM cell arrangement in which each memory cell (1) has a memory capacitor (2) and a read-out transistor (3). A buried strap contact (11) for connecting to the read-out transistor is produced by diffusing dopants out of the electrode of the memory capacitor (2). Said buried strap contact (11) is superposed by the implantations (12) of the source/drain area (5) of the read-out transistor (3), said implantation (12) of the source/drain area (5) forming the boundary of the space charge region of a p/n transition of the memory cell (1).

    Abstract translation: 本发明涉及一种DRAM单元结构中，其中相应的存储单元，包括存储电容器（1）（2）和读出晶体管（3）。 用于连接到所述读出晶体管由掺杂剂向外扩散从存储电容器（2）埋层带接触（11）的电极产生的。 所述埋层带接触（11）是通过源的注入（12）/漏区（5）的选择晶体管（3）的叠加，从而使光源的植入物（12）/漏区（5），空间电荷区的边界 形成存储器单元（1）的p / n结。

    CONTACT FOR A TRENCH CAPACITOR OF A DRAM CELL ARRANGEMENT
    2.
    发明申请
    CONTACT FOR A TRENCH CAPACITOR OF A DRAM CELL ARRANGEMENT 审中-公开
    联系方式欲抢电容器DRAM ZELLA ORDER

    公开(公告)号：WO0139248A8

    公开(公告)日：2002-03-28

    申请号：PCT/DE0003987

    申请日：2000-11-14

    Applicant: INFINEON TECHNOLOGIES AG ,  BENZINGER HERBERT ,  RICHTER FRANK

    Inventor： BENZINGER HERBERT ,  RICHTER FRANK

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/10867

    Abstract: The invention relates to a DRAM cell arrangement in which each memory cell (1) has a memory capacitor (2) and a read-out transistor (3). A buried strap contact (11) for connection to the read-out transistor is produced by diffusing dopants out of the electrode of the memory capacitor (2). Said buried strap contact (11) is superposed by the implantations (12) of the source/drain area (5) of the read-out transistor (3), said implantations (12) of the source/drain area (5) forming the boundary of the space charge region of a p/n transition of the memory cell (1). As a result, the generation centres and defects in a buried strap contact are eliminated more than a diffusion length for minority carriers from the space charge region of a p/n transition. Minority carriers of this type then recombine before they reach the p/n transition and are electrically ineffective. This considerably reduces the leakage currents across the p/n transition and increases the retention time.

    Abstract translation: 本发明涉及一种DRAM单元结构中，其中相应的存储单元，包括存储电容器（1）（2）和读出晶体管（3）。 用于连接到所述读出晶体管由掺杂剂向外扩散从存储电容器（2）埋层带接触（11）的电极产生的。 所述埋层带接触（11）是通过源的注入（12）/漏区（5）的选择晶体管（3）的叠加，从而使光源的植入物（12）/漏区（5），空间电荷区的边界 形成存储器单元（1）的p / n结。 这实现了在以比从除去的p / n结的耗尽区少数载流子的扩散长度以上的埋层带接触的产生中心和缺陷。 因此，才可以到达p / n结，并且因此电惰性重新结合，例如少数载流子。 这意味着漏电流在p / n结的显着降低，并且因此提高蛋的保留时间。

    MEMORY WITH A TRENCH CAPACITOR AND A SELECTION TRANSISTOR AND METHOD FOR PRODUCING THE SAME
    3.
    发明申请
    MEMORY WITH A TRENCH CAPACITOR AND A SELECTION TRANSISTOR AND METHOD FOR PRODUCING THE SAME 审中-公开
    具有集群电容器和选择晶体管的存储器及其制造方法

    公开(公告)号：WO0117019A3

    公开(公告)日：2001-05-10

    申请号：PCT/DE0002866

    申请日：2000-08-23

    Applicant: INFINEON TECHNOLOGIES AG ,  TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

    Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10861 ,  H01L27/10832

    Abstract: The invention comprises a memory with a storage cell (100) that is formed in a substrate (105) and consists of a trench capacitor (110) and a transistor (160). The trench capacitor (110) is connected to the transistor (160) with a self-aligned connection (220). The transistor (160) at least partially covers said trench capacitor (110). The trench capacitor (110) is filled with a conductive trench filling and an insulating cover layer (135) is located on said conductive trench filling (130). An epitaxy layer (245) is located above said insulating cover layer (135). The transistor (160) is formed in said epitaxy layer (245). The self-aligned connection (220) is formed in a contact trench (205) and consists of an insulation collar (235) into which a conductive material (225) is introduced. A conductive cap (230) is formed on said conductive material.

    Abstract translation: 本发明包括具有存储单元（100）的存储器，存储单元（100）形成在衬底（105）中并由沟槽电容器（110）和晶体管（160）组成。 沟槽电容器（110）通过自对准端子（220）连接到晶体管（160）。 晶体管（160）至少部分地覆盖沟槽电容器（110）。 沟槽电容器（110）填充有导电沟槽填充物（130），并且在导电沟槽填充物（130）上是绝缘覆盖层（135）。 绝缘覆盖层（135）之上是外延层（245）。 晶体管（160）形成在外延层（245）中。 自对准端子（220）形成在接触沟槽（205）中并且由其中引入导电材料（225）的绝缘轴环（235）组成。 在导电材料上形成导电帽（230）。

    5.
    发明专利
    未知

    公开(公告)号：DE102004010704B3

    公开(公告)日：2005-10-13

    申请号：DE102004010704

    申请日：2004-03-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PROELL MANFRED ,  SCHROEDER STEPHAN ,  KLIEWER JOERG ,  BENZINGER HERBERT

    IPC: G11C7/12 ,  G11C11/00 ,  G11C11/4094

    Abstract: An integrated semiconductor memory device includes a memory cell array (B 1 ) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit ( 100 ) configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET 1 ) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A 10 ) that applies a mid-voltage (V BLEQ ), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (V BLEQ ) is shortened. The influence of capacitive coupling influences, which slow down the charging of the first and second bit lines to the mid-voltage, is significantly reduced as a result.

    6.
    发明专利
    未知

    公开(公告)号：DE10335618A1

    公开(公告)日：2005-03-10

    申请号：DE10335618

    申请日：2003-08-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DOBLER MANFRED ,  BENZINGER HERBERT ,  KLIEWER JOERG ,  PROELL MANFRED

    IPC: G11C8/08 ,  G11C11/406 ,  G11C11/408 ,  G11C11/407

    Abstract: A semiconductor memory includes storage cells ( 2 ) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V 1, V 2 ) in order to open and close the transistor. The electrode potential (V 2 ) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory ( 1 ) so that the second electrical potential (V 2 ) becomes more different from the first electrical potential (V 1 ) as the temperature (T) increases.

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