公开(公告)号：JP2003023110A

公开(公告)日：2003-01-24

申请号：JP2002159754

申请日：2002-05-31

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： RICHTER FRANK ,  TEMMLER DIETMAR

IPC: G11C7/00 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10832

Abstract: PROBLEM TO BE SOLVED: To provide memory cell structure having memory cells guaranteeing the simple connection of a small necessary area.
SOLUTION: The memory cells (15a, 15b and 15c) which are regularly arranged on a semiconductor piece are provided with trench capacitors (20a, 20b and 20c) formed on a semiconductor substrate (10), selection transistors (30a, 30b and 30c) formed on the capacitors and self-matching selection transistors (301, 30b and 30c)/memory trench contact parts (40a and 40b)/trench insulating part (52) structures.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供具有保证小的必要区域的简单连接的存储单元的存储单元结构。 解决方案：规则地布置在半导体片上的存储单元（15a，15b和15c）设置有形成在半导体衬底（10）上的沟槽电容器（20a，20b和20c），选择晶体管（30a，30b和30c） 形成在电容器和自匹配选择晶体管（301,30b和30c）/存储器沟槽接触部分（40a和40b）/沟槽绝缘部分（52）结构上。

公开(公告)号：JP2001298062A

公开(公告)日：2001-10-26

申请号：JP2001047190

申请日：2001-02-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RICHTER FRANK

IPC: G01R31/26 ,  H01L21/66 ,  H01L23/544

Abstract: PROBLEM TO BE SOLVED: To increase the number of individual structures or inspecting components that can inspect a chip surface of an integrated circuit. SOLUTION: The inspecting components are a plurality of transistors. At least two transistors are placed between two adjacent contact surfaces and are connected to the adjacent contact surfaces. Thus, voltage can be applied to the transistors via the contact surfaces, and gate terminals of the transistors are connected to another contact surface to supply switching current.

公开(公告)号：WO0139248A2

公开(公告)日：2001-05-31

申请号：PCT/DE0003987

申请日：2000-11-14

Applicant: INFINEON TECHNOLOGIES AG ,  BENZINGER HERBERT ,  RICHTER FRANK

Inventor： BENZINGER HERBERT ,  RICHTER FRANK

IPC: H01L27/108 ,  H01L21/8242 ,  H01L

CPC classification number: H01L27/10867

Abstract: The invention relates to a DRAM cell arrangement in which each memory cell (1) has a memory capacitor (2) and a read-out transistor (3). A buried strap contact (11) for connecting to the read-out transistor is produced by diffusing dopants out of the electrode of the memory capacitor (2). Said buried strap contact (11) is superposed by the implantations (12) of the source/drain area (5) of the read-out transistor (3), said implantation (12) of the source/drain area (5) forming the boundary of the space charge region of a p/n transition of the memory cell (1).

Abstract translation: 本发明涉及一种DRAM单元结构中，其中相应的存储单元，包括存储电容器（1）（2）和读出晶体管（3）。 用于连接到所述读出晶体管由掺杂剂向外扩散从存储电容器（2）埋层带接触（11）的电极产生的。 所述埋层带接触（11）是通过源的注入（12）/漏区（5）的选择晶体管（3）的叠加，从而使光源的植入物（12）/漏区（5），空间电荷区的边界 形成存储器单元（1）的p / n结。

公开(公告)号：WO02101824A3

公开(公告)日：2003-08-28

申请号：PCT/DE0202046

申请日：2002-06-05

Applicant: INFINEON TECHNOLOGIES AG ,  RICHTER FRANK ,  TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

Inventor： RICHTER FRANK ,  TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10832 ,  H01L27/10873

Abstract: A memory cell (10) is embodied with a selection transistor (60) and a trench capacitor (30). The trench capacitor (30) is filled with a conducting trench filling (35), upon which an insulating cover layer (40) is arranged. A selectively grown epitaxial layer (45) is laterally grown over the insulating cover layer, starting from the substrate (15). The selection transistor (60) is embodied in the selectively grown epitaxial layer (45) and comprises a source region (65), for connection to the trench capacitor (30) and a drain region (70) for connection to a bitline. The junction depth of the source region (65) is selected such that the source region (65) extends as far as the insulating cover layer (40). In addition the thickness (50) of the epitaxial layer (45) may be optionally reduced to a suitable thickness by means of an oxidation and a subsequent etching. A contact trench (95) is then etched through the source region (65) as far as the conducting trench filling (35), which is filed with a conducting contact (90) and the conducting trench filling (35) electrically connected to the source region (65).

Abstract translation: 形成有具有选择晶体管（60）和一个电容器严重（30）的存储单元（10）。 坟墓电容器（30）被填充有导电填充严重（35），在其上的绝缘层（40）被布置。 覆盖绝缘层是横向地，从基板（15）配有一个选择性地生长外延层（45）生长开始。 在选择晶体管的选择性生长的外延层（45）（60）形成，并且在这种情况下包括连接到位线的源极区（65）以与严重电容器（30）连接，并且漏极区域（70） 要被连接的。 源极区（65）的结深度现在被选择为使得源极区（65）延伸直到所述绝缘覆盖层（40）。 任选地，通过氧化和随后的蚀刻的装置的外延层（45）的厚度（50）可以减少到适当的厚度。 接着，通过接触沟槽（95），以在导电严重填充所述源极区（65）（35）被蚀刻时，其被填充有导电接触（90）和所述导电严重填充（35）电性（与源极区域 65）连接。

公开(公告)号：WO0139248A8

公开(公告)日：2002-03-28

申请号：PCT/DE0003987

申请日：2000-11-14

Applicant: INFINEON TECHNOLOGIES AG ,  BENZINGER HERBERT ,  RICHTER FRANK

Inventor： BENZINGER HERBERT ,  RICHTER FRANK

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10867

Abstract: The invention relates to a DRAM cell arrangement in which each memory cell (1) has a memory capacitor (2) and a read-out transistor (3). A buried strap contact (11) for connection to the read-out transistor is produced by diffusing dopants out of the electrode of the memory capacitor (2). Said buried strap contact (11) is superposed by the implantations (12) of the source/drain area (5) of the read-out transistor (3), said implantations (12) of the source/drain area (5) forming the boundary of the space charge region of a p/n transition of the memory cell (1). As a result, the generation centres and defects in a buried strap contact are eliminated more than a diffusion length for minority carriers from the space charge region of a p/n transition. Minority carriers of this type then recombine before they reach the p/n transition and are electrically ineffective. This considerably reduces the leakage currents across the p/n transition and increases the retention time.

Abstract translation: 本发明涉及一种DRAM单元结构中，其中相应的存储单元，包括存储电容器（1）（2）和读出晶体管（3）。 用于连接到所述读出晶体管由掺杂剂向外扩散从存储电容器（2）埋层带接触（11）的电极产生的。 所述埋层带接触（11）是通过源的注入（12）/漏区（5）的选择晶体管（3）的叠加，从而使光源的植入物（12）/漏区（5），空间电荷区的边界 形成存储器单元（1）的p / n结。 这实现了在以比从除去的p / n结的耗尽区少数载流子的扩散长度以上的埋层带接触的产生中心和缺陷。 因此，才可以到达p / n结，并且因此电惰性重新结合，例如少数载流子。 这意味着漏电流在p / n结的显着降低，并且因此提高蛋的保留时间。

公开(公告)号：DE10131237B4

公开(公告)日：2006-05-04

申请号：DE10131237

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  RICHTER FRANK ,  POPP MARTIN ,  WICH-GLASEN ANDREAS

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

Abstract: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current I ON can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

公开(公告)号：DE19957540B4

公开(公告)日：2005-07-07

申请号：DE19957540

申请日：1999-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RICHTER FRANK ,  TEMMPLER DIETER

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L21/266 ,  H01L21/8242

Abstract: A simple method for fabricating a field-effect transistor having an anti-punch-through implantation region is provided. After the anti-punch-through implantation region is formed, a semiconductor substrate is locally oxidized by using a mask layer in order to form a gate insulation layer. The method allows the fabrication of field-effect transistors having improved short-channel properties.

公开(公告)号：DE10010285A1

公开(公告)日：2001-09-13

申请号：DE10010285

申请日：2000-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RICHTER FRANK

IPC: G01R31/26 ,  H01L21/66 ,  H01L23/544 ,  H01L29/78

Abstract: With increasing integration density of integrated circuits, the packing density in test regions (kerf structures) located between the integrated circuits cannot be increased substantially, since the majority of the available area is occupied by contact areas. The invention is therefore directed toward a test structure region on a wafer having contact areas for applying voltages and test components between the contact areas. The test structure includes at least two test components that are arranged between two adjacent contact areas. The test components are each connected to the adjacent contact areas so that a voltage can be applied to the test components via the contact areas.

公开(公告)号：DE19957540A1

公开(公告)日：2001-06-13

申请号：DE19957540

申请日：1999-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RICHTER FRANK ,  TEMMPLER DIETER

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L21/266 ,  H01L21/8242

Abstract: A simple method for fabricating a field-effect transistor having an anti-punch-through implantation region is provided. After the anti-punch-through implantation region is formed, a semiconductor substrate is locally oxidized by using a mask layer in order to form a gate insulation layer. The method allows the fabrication of field-effect transistors having improved short-channel properties.

公开(公告)号：DE10043350A1

公开(公告)日：2002-04-04

申请号：DE10043350

申请日：2000-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GERSTMEIER GUENTER ,  RICHTER FRANK ,  ROSSKOPF VALENTIN

IPC: G11C29/00 ,  H01L23/544 ,  H01L21/66

Abstract: A process for studying structures on a wafer which have been produced using a light mask on the wafer comprises having the test circuits (4) and test structures placed on the mask in a given reference position. The test and/or the illumination process evaluate a place-dependent electrical parameter.