公开(公告)号：WO2004025693A3

公开(公告)日：2004-04-29

申请号：PCT/EP0308946

申请日：2003-08-12

Applicant: INFINEON TECHNOLOGIES AG ,  ENDERS GERHARD ,  FAUL JUERGEN ,  FISCHER BJOERN ,  HEINECK LARS ,  HIERLEMANN MATTHIAS ,  POPP MARTIN ,  VOIGT PETER

Inventor： ENDERS GERHARD ,  FAUL JUERGEN ,  FISCHER BJOERN ,  HEINECK LARS ,  HIERLEMANN MATTHIAS ,  POPP MARTIN ,  VOIGT PETER

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242

CPC classification number: H01L27/10873 ,  H01L21/26586 ,  H01L27/10888 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66659

Abstract: The invention relates to a method for the production of a semi-conductor structure comprising a plurality of gate stacks (GS1 - GS8) which are arranged on a semi-conductor substrate (1). Said method comprises the following steps: applying the gate-stack (GS1 - GS8) to a gate dielectric (5) via the semi-conductor substrate (1); implanting doping (100, 105, 110, 120, 130; 105''', 110''', 120''', 130''', 140''') which is self-adjusted in relation to the edges of the gate stack (GS1 - GS8); and forming an side wall oxide (40) on the free side walls of the gate stack (GS1 - GS8) while at the same time forming diffused doping areas (100', 110', 120', 130'; 110''', 120''', 130''', 140''') below the gate stack. The invention also relates to said type of semi-conductor structure.

Abstract translation: 本发明提供了一种用于生产具有多个栅极堆栈（GS1 - GS8）的半导体结构的半导体衬底（1）上通过以下步骤制备：将所述栅极堆叠 - 上的栅极电介质（GS1 GS8）（5 ）在半导体衬底上（1）; 注入掺杂剂（100，105，110，120，130; 105 '' '110' ''，120 '''，130' ''，140 ''“）自对准到栅叠层的边缘（GS1 - GS8 ）; 以及形成在所述栅极堆叠（GS1 - GS8）的暴露的侧壁上形成侧壁氧化物（40）与扩散掺杂区的同时形成（100 '110' ，120'，130 '; 110 '''，120' ''，130 “”栅极边缘下”，140' ‘’）。 本发明还提供这样的半导体结构。

公开(公告)号：WO03028104A3

公开(公告)日：2003-08-14

申请号：PCT/DE0202980

申请日：2002-08-14

Applicant: INFINEON TECHNOLOGIES AG ,  LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

Inventor： LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10891

Abstract: A trench capacitor (30) is arranged in a first trench (25) for production of a semiconductor memory (5). A first longitudinal trench (55) is arranged in the substrate (15) next to the first trench (25) and parallel thereto on the other side of the first trench (25), a second longitudinal trench (60) is arranged therein. A first spacer word line (70) is arranged in the first longitudinal trench (55) and a second spacer word line (75) is arranged in the second longitudinal trench (60). Connecting webs (80) are arranged in the first trench (25) between the first spacer word line (70) and the second spacer word line (75) with a thickness (110), which is smaller in the direction of the first spacer word line (70) than half the width of the first trench (25) in the direction of the first spacer word line (70).

Abstract translation: 为了制造半导体存储器（5），沟槽电容器（30）被布置在第一沟槽（25）中。 除了所述第一沟槽（25），第一纵向沟槽（55）和上第一沟槽并行（25），在所述基板的第二纵向沟槽（60）的另一侧（15）被布置。 在第一纵向沟槽（55）中设置第一间隔字线（70），在第二纵向沟槽（60）中设置第二间隔字线（75）。 在所述第一沟槽（25）的连接板（80）设置在所述第一间隔物的字线（70）和具有厚度（110）所述第二间隔的字线（75）（在第一间隔的字线70的方向之间 ）小于第一沟槽（25）朝向第一间隔字线（70）的宽度的一半。

公开(公告)号：WO0211200A8

公开(公告)日：2002-04-11

申请号：PCT/DE0102798

申请日：2001-07-23

Applicant: INFINEON TECHNOLOGIES AG ,  GOEBEL BERND ,  LUETZEN JOERN ,  POPP MARTIN ,  SEIDL HARALD

Inventor： GOEBEL BERND ,  LUETZEN JOERN ,  POPP MARTIN ,  SEIDL HARALD

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864

Abstract: The invention relates to a semiconductor memory cell arrangement comprising dynamic memory cells (10) which each have a trench capacitor (1) and a vertical selection transistor (2). Said vertical selection transistor (2) is situated essentially above the trench capacitor (1) and has a series of layers which is offset from the inner electrode of the trench capacitor (1) and which is connected to said inner electrode (11) of the trench capacitor (1). An active intermediate layer (22) is completely surrounded by an insulator layer (24) and a gate electrode layer (25) which is connected to a word line (7). The dynamic memory cells (10) are arranged in the form of a matrix, the trench capacitors (1) and the corresponding vertical selection transistors (2) of the dynamic memory cells (10) succeeding each other in a line and/or column sequence, respectively.

Abstract translation: 具有动态存储单元的半导体存储器单元阵列（10），每一个都具有严重的电容器（1）和一个verikalen选择晶体管（2），其特征在于，垂直选择晶体管（2）基本上高于WOM严重电容器（1）被布置和相对的内部电极 被严重电容器（1）与一个布置成与严重电容器（1），其特征在于，有源中间层（22）被封闭具有完全的绝缘体层（24）和栅电极层（25）的内电极（11）偏移的层序列 Worleitung（7）连接，其中，所述动态存储单元（10）被布置成矩阵，和坟墓电容器（1）和相关联的垂直选择Transistore（2）的动态存储器单元（10），每行和/或列状连续的。

公开(公告)号：WO03081666A8

公开(公告)日：2005-05-12

申请号：PCT/EP0301139

申请日：2003-02-05

Applicant: INFINEON TECHNOLOGIES AG ,  LUETZEN JOERN ,  POPP MARTIN ,  SCHLOESSER TILL

Inventor： LUETZEN JOERN ,  POPP MARTIN ,  SCHLOESSER TILL

IPC: H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10888 ,  H01L21/28525 ,  H01L21/76895 ,  H01L21/76897

Abstract: The invention relates to a production method for a contact in a semiconductor structure comprising a substrate (1) provided with a first and second structural element (GS1, GS2) of approximately the same height which are disposed on the surface of the substrate and which are distanced from each other by means of an intermediate space having a critical lateral dimension. The inventive method comprises the following steps: provision of an active area (60) in the substrate (1) between the structural elements (GS1, GS2); raising the active area (60) by selective epitaxy of conductive substrate material (80); and formation of the contact (CB) on the raised active area. The invention also relates to a corresponding contact.

Abstract translation: 本发明提供在半导体结构中的接触包括具有第一和第二在设置于基材表面大约等于高的结构元件（GS1，GS2），基板（1）的制造方法，其彼此通过用临界的横向尺寸的间隙 被间隔开，其包括以下步骤：在所述的结构元件（GS1，GS2）之间的基板（1）提供的有源区（60）; 有源区（60）由导电性衬底材料的选择性生长（80）的增加; 以及形成在凸起有源区的接触（CB）。 本发明还提供了相应的接触。

公开(公告)号：DE10334547B4

公开(公告)日：2006-07-27

申请号：DE10334547

申请日：2003-07-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUDELKA STEPHAN ,  SAENGER ANNETTE ,  SEIDL HARALD ,  POPP MARTIN

IPC: H01L21/8242 ,  H01L21/20 ,  H01L21/334 ,  H01L27/108

公开(公告)号：DE10334547A1

公开(公告)日：2005-03-10

申请号：DE10334547

申请日：2003-07-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUDELKA STEPHAN ,  SAENGER ANNETTE ,  SEIDL HARALD ,  POPP MARTIN

IPC: H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：DE10214126A1

公开(公告)日：2003-10-23

申请号：DE10214126

申请日：2002-03-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WICH-GLASEN ANDREAS ,  POPP MARTIN

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234

Abstract: Process for producing a plurality of gate stacks approximately the same height and equidistant on a semiconductor substrate. The process includes providing a gate dielectric on the semiconductor substrate and applying and patterning at least a first layer and a second layer, above the first layer, to the gate dielectric to produce the gate stacks. An oblique implantation of an oxidation-inhibiting implantation species is carried out into two opposite, uncovered side faces of the second of the gate stacks, with respectively adjacent gate stacks serving to shadow the uncovered side faces of the first layer of the gate stacks. Oxidation to simultaneously form a first oxide layer on uncovered side faces of the first layer of the gate stacks and a second oxide layer on uncovered side faces of the second layer of the gate stacks is carried out, the thickness of the first oxide layer being greater than the thickness of the second oxide layer.

公开(公告)号：DE10152549A1

公开(公告)日：2003-05-15

申请号：DE10152549

申请日：2001-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  WICH-GLASEN ANDREAS ,  TEMMLER DIETMAR

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: Production of electrical contact region in micro-electronic semiconductor structure comprises: producing trench in substrate; forming insulating layer partially covering the trench wall and filling the trench with electrically conductive filler; removing the first filler from the trench up to a required depth a; removing the insulating layer up to a depth b; and forming electrical contact region. Production of an electrical contact region in a micro-electronic semiconductor structure comprises: producing a trench (4) in a substrate (1); forming an insulating layer (9) partially covering the trench wall and filling the trench with an electrically conducting filler (10); removing the first filler from the trench up to a required depth a; removing the insulating layer up to a depth b which is deeper than depth a; and forming an electrical contact region (13, 14) on the edge regions of the trench, in which the insulating layer is removed, in the region between the depth b up to the maximum to a processed upper edge of the filling of the trench. Preferred Features: The processed upper edge of the filling of the trench is produced through the surface of the first filler. An intermediate layer having a thickness d is deposited on the horizontal surface of the first filler through which the processed upper edge of the filling of the trench is produced.

公开(公告)号：DE10131237B4

公开(公告)日：2006-05-04

申请号：DE10131237

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  RICHTER FRANK ,  POPP MARTIN ,  WICH-GLASEN ANDREAS

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

Abstract: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current I ON can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

公开(公告)号：DE10226965B4

公开(公告)日：2006-04-20

申请号：DE10226965

申请日：2002-06-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MANGER DIRK ,  POPP MARTIN ,  SCHLOESSER TILL ,  SESTERHENN MICHAEL

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

Abstract: In semiconductor memories, in particular DRAMs, the memory cells of which have vertical transistors at vertical lands formed from substrate material, gate electrodes are formed as spacers which run around the land. The gate electrodes of adjacent memory cells conventionally have to be retroactively connected to form word lines. It is known to fill spaces between adjacent lands with an oxide, with the result that the spacers are formed directly as word lines but only cover two side walls of a land. Two transistors which are connected in parallel are formed at these side walls instead of a single transistor, since the gate electrode does not run around the land. The invention proposes a method for fabricating a semiconductor memory in which all four side walls of a land are covered by the word lines and at the same time lands of adjacent memory cells are connected to one another by the word lines.