公开(公告)号：WO02075551A3

公开(公告)日：2003-08-28

申请号：PCT/DE0200549

申请日：2002-02-15

Applicant: INFINEON TECHNOLOGIES AG ,  KNIFFLER OLIVER ,  SEDLAK HOLGER

Inventor： KNIFFLER OLIVER ,  SEDLAK HOLGER

IPC: G06F13/42

CPC classification number: G06F13/4217

Abstract: The invention relates to a data bus which can be operated in a multiplex mode, whereby at least one control station and a receiving station are connected thereto. A control bus is also provided, through which a logical channel is allocated by the control station to the receiving station. Once logical channel has been allocated, the address does not have to be transferred via the data bus before the receiving station is next addressed. The receiving station monitors the control bus and is addressed so that the allocated logical channel of the receiving station is opened therewith.

Abstract translation: 它是在一个多路复用数据总线可操作提供，在其上至少一个控制站和接收站连接。 有另外从控制站到接收站提供的控制总线，逻辑信道可以在所分配的。 如果分配一旦做出，必须为地址经由数据总线接收站不仅下一激活之前被发送。 接收站监视控制总线和被寻址尽快与该接收站逻辑信道是开放的分配。

公开(公告)号：WO02099809A2

公开(公告)日：2002-12-12

申请号：PCT/EP0206145

申请日：2002-06-04

Applicant: INFINEON TECHNOLOGIES AG ,  DIRSCHERL GERD ,  HARTLIEB HEIMO ,  MAY CHRISTIAN ,  SEDLAK HOLGER

Inventor： DIRSCHERL GERD ,  HARTLIEB HEIMO ,  MAY CHRISTIAN ,  SEDLAK HOLGER

IPC: G11C8/20

CPC classification number: G11C8/20

Abstract: The invention relates to a method for controlling the mapping of a logical address of a logical address space to a physical address of a physical address space (20). Said method involves the following steps: a first physical address and a corresponding memory cell, which are associated by the mapping (30) of a logical address, are determined; the memory cell is checked for serviceability; and the mapping (30) is modified if the check reveals that the memory cell is not serviceable, in such a way that the logical address is mapped to a second physical address in the physical address space (20). In this way, access to a physical memory is carried out by means of logical addresses which are mapped to the physical addresses of the physical memory, i.e. virtual memory addressing is used in order to mask out non-serviceable memory cells in a simple and effective manner.

Abstract translation: 为一个逻辑地址空间的逻辑地址的图像的用于控制到物理地址空间（20）的物理的本发明的方法包括：确定经由所述映射与逻辑地址相关联的第一物理地址和相关联的存储单元（30），检查 存储器单元自己的能力发挥功能并改变所述映射（30），如果检查的步骤示出了存储单元是无功能的，因此，逻辑地址被映射到物理地址空间（20）的第二物理地址。 以这种方式，通过由一个映射映射到物理存储器，即物理地址的逻辑地址的装置进行访问的物理存储器 虚拟存储器寻址，用于以简单和有效的方式筛选出的非功能存储单元。

公开(公告)号：WO02099645A2

公开(公告)日：2002-12-12

申请号：PCT/EP0205319

申请日：2002-05-14

Applicant: INFINEON TECHNOLOGIES AG ,  GAMMEL BERNDT ,  SEDLAK HOLGER ,  MAY CHRISTIAN ,  LEDWA RALPH

Inventor： GAMMEL BERNDT ,  SEDLAK HOLGER ,  MAY CHRISTIAN ,  LEDWA RALPH

IPC: G06F12/1009 ,  G06F12/00

CPC classification number: G06F12/1009 ,  G06F2212/651 ,  G06F2212/681

Abstract: The invention relates to a method for determining a physical address from a virtual address, whereby a mapping rule is implemented between the virtual address and the physical address in the form of a hierarchical tree structure comprising compressed nodes. According to said method, a compression indicator contained in the mapping rule is first read (1300). Then, a section of the virtual address, which is assigned to the node level under consideration, is read (1310). An entry in the node list of the node currently under consideration is determined (1320) using the compression indicator and the virtual address section. The entry that has been determined is read (1330) and the physical address can then be directly determined, if the node level under consideration was the lowest node level in the hierarchy. If there are additional node levels to be processed, the previous steps are repeated for the determination (1340) of the physical address for compressed nodes of lower hierarchy levels, until the lowest node level in the hierarchy has been reached. For addressing schemes, in which the virtual address space is greater than the physical address space, storage space can be saved by the compression of the node lists, which in their uncompressed form contain a number of zero entries, thus providing space for other data.

Abstract translation: 在用于从虚拟地址确定物理地址的方法，其中，所述虚拟地址和物理地址之间的映射规则为具有节点压缩时，容纳在所述映射规则压缩指示器被第一读（1300）的分层树结构来实现。 另外，所考虑的节点电平相关联的所述虚拟地址的一部分被读取（1310）。 使用压缩指示符和虚拟地址的一部分，在当前考虑的节点的节点列表中的条目被确定（1320）。 所确定的条目被读取（1330），在此之后，物理地址可以直接确定，如果考虑的节点电平是最低分层节点级别。 如果需要的话，进一步被加工节面都存在时，确定（1340）的物理地址时为较低层次的压缩节点重复先前的步骤直到达到最低层次级的节点。 在寻址方案，其中，所述虚拟地址空间是大于物理地址空间大的可通过压缩解压缩，包括壳体节点列表而获得，多个零个条目，存储空间可以被保存并用于其他的数据可用。

公开(公告)号：WO02067108A3

公开(公告)日：2002-12-12

申请号：PCT/EP0200719

申请日：2002-01-24

Applicant: INFINEON TECHNOLOGIES AG ,  ELBE ASTRID ,  SEDLAK HOLGER ,  JANSSEN NORBERT ,  SEIFERT JEAN-PIERRE

Inventor： ELBE ASTRID ,  SEDLAK HOLGER ,  JANSSEN NORBERT ,  SEIFERT JEAN-PIERRE

IPC: G06F7/72

CPC classification number: G06F7/722 ,  G06F7/724

Abstract: A multiplication forecast method (210) is executed in order to obtain a multiplication shift value (s>z z ) arithmetic on a single long number arithmetic-logic unit.

Abstract translation: 执行乘法先行方法（210），以获得一乘法位移值（SZ）。 中间结果多项式（Z）由乘法位移值（SZ）向左（214）。此外，还原先行方法（212）导向装置的位数移位。 于是，模数多项式等于由数量的减少位移值（216）的数字移位。 在三操作数加法（218）的中间结果版本插入polinom（Z“）是和所述被乘数（C）被相加，和该移模数多项式（N”）被减去。 由进位关控制功能，因此能够同时执行Z / NZ算术以及一个GF（2 n）的算术单长数算术逻辑单元上。

公开(公告)号：WO0219065A8

公开(公告)日：2002-09-26

申请号：PCT/EP0109285

申请日：2001-08-10

Applicant: INFINEON TECHNOLOGIES AG ,  SEDLAK HOLGER ,  SEIFERT JEAN-PIERRE

Inventor： SEDLAK HOLGER ,  SEIFERT JEAN-PIERRE

IPC: G06F7/72 ,  G06F12/14 ,  G06F21/55 ,  G06F1/00

CPC classification number: H04L9/002 ,  G06F7/723 ,  G06F12/145 ,  G06F21/755 ,  G06F2207/7257 ,  G06F2207/7271 ,  H04L9/302

Abstract: The invention relates to a method for producing security modules with virtual memory addressing whereby logical addresses are mapped uniquely onto physical addresses using a mapping specification (30). The method comprises the provision of a first security module with a first mapping specification and the provision of a second security module with a second mapping specification which is different from the first mapping specification. The particularity of the virtual memory address, i.e. the invariancy of the programme address space from the actual physical address space or from the mapping specification (30) of the programme address space in the physical address space is used insofar as for security modules that are otherwise identical, the stored information, e.g. an application code or application data, are stored in different physical addresses at two different points in time in a comparison between two different security modules and/or in a comparison of one security module. This increases the security of the security module with respect to attacks.

公开(公告)号：WO0153931A3

公开(公告)日：2001-12-20

申请号：PCT/DE0100018

申请日：2001-01-05

Applicant: INFINEON TECHNOLOGIES AG ,  GAMMEL BERNDT ,  KNIFFLER OLIVER ,  SEDLAK HOLGER

Inventor： GAMMEL BERNDT ,  KNIFFLER OLIVER ,  SEDLAK HOLGER

IPC: G06F12/08 ,  G06F12/14 ,  G06F15/78 ,  G06F21/75

CPC classification number: G06F21/75 ,  G06F12/1408

Abstract: A microprocessor system wherein data is temporarily stored in a cache memory (8) or a register bank (9). A respectively allocated cryptographic unit (81, 82; 91) is responsible for encrypting/decrypting the data when the cache memory (8) or register bank is accessed. The code word used therefor is modified when the cache memory (8) or register (9) no longer contains any data which is to be read. This results in increased security with respect to unauthorized access to data and program execution.

Abstract translation: 在微处理器中的配置数据被暂时存储在高速缓冲存储器（8）或寄存器组（9）。 甲分别相关联的加密单元（81，82; 91）提供在到高速缓冲存储器（8）或寄存器组（9）的访问的数据的加密/解密。 当要读出的高速缓冲存储器（8）或寄存器（9）不包含有效数据的详细这里使用的密钥字被改变。 这提供了防止间谍更高的安全性上的数据，并且获得的程序流。

公开(公告)号：DE102005052293B4

公开(公告)日：2013-08-14

申请号：DE102005052293

申请日：2005-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEDLAK HOLGER ,  OTTERSTEDT JAN

IPC: G11C11/406 ,  G06F12/16

Abstract: Speicherschaltung (100) mit folgenden Merkmalen: eine Mehrzahl von Speicherbereichen (120), deren Reihenfolge von jeweils zugeordneten logischen Adressen (LA) abhängt und denen jeweils ein Kontrollwert (DH) zugeordnet ist; eine Einrichtung (150), die Informationen enthält, welche Speicherbereiche (120) benutzt sind; und eine Steuereinrichtung (130), die so ausgelegt ist, dass sie beim Schreiben in einen Zielspeicherbereich der Mehrzahl von Speicherbereichen (120) – dem dem Zielspeicherbereich zugeordneten Kontrollwert (DH) einen Wert gibt, der dem einem niedrigsten benutzten Speicherbereich (120) zugeordneten Kontrollwert (DH) entspricht, wenn ein benutzter Speicherbereich (120) existiert, und einen beliebigen oder vorgegebenen Wert gibt, wenn kein benutzter Speicherbereich (120) existiert; und – wenn eine Bedingung erfüllt ist, und wenn zumindest zwei benutzte Speicherbereiche (120) existieren, – Neuschreiben des Inhalts eines nächsten Speicherbereichs (120), dessen Kontrollwert (DH) zu dem Kontrollwert (DH) des niedrigsten Speicherbereichs (120) eine Beziehung aufweist, und Ändern des Kontrollwerts (DH) des nächsten Speicherbereichs (120), wenn ein solcher nächster Speicherbereich (120) existiert; und – Neuschreiben des Inhalts des niedrigsten Speicherbereichs (120) und Ändern des demselben zugeordneten Kontrollwerts (DH), wenn ein nächster Speicherbereich (120), dessen Kontrollwert (DH) zu dem Kontrollwert (DH) des niedrigsten Speicherbereichs (120) die Beziehung aufweist, nicht existiert.

公开(公告)号：AT505763T

公开(公告)日：2011-04-15

申请号：AT02701240

申请日：2002-01-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUECKLMAYR FRANZ-JOSEF ,  FRIEDINGER HANS ,  SEDLAK HOLGER ,  MAY CHRISTIAN

IPC: G06F12/14 ,  G06F21/24

Abstract: A microprocessor circuit for organizing access to data or programs stored in a memory has a microprocessor, a memory for storing an operating system, and a memory for storing individual external programs. A plurality of memory areas with respective address spaces is provided in the memory for storing the external programs. Each address space is assigned an identifier. The identifier assigned to a memory area is loaded into a first auxiliary register prior to the addressing of the memory area and the identifier of the addressed memory area is loaded into a second auxiliary register. A comparison of the contents of the first and second auxiliary registers is performed. Furthermore, each address space of a memory area is assigned at least one bit sequence defining access rights, whereby code instructions and sensitive data can be protected against write accesses from other external programs.

公开(公告)号：DE50014967D1

公开(公告)日：2008-03-27

申请号：DE50014967

申请日：2000-07-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BADER MARTIN ,  BRUECKLMAYR FRANZ-JOSEF ,  REINER ROBERT ,  SCHRAUD GERHARD DR ,  SEDLAK HOLGER

IPC: G06K19/07

公开(公告)号：DE10357749B4

公开(公告)日：2007-12-20

申请号：DE10357749

申请日：2003-12-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEDLAK HOLGER ,  GOETTFERT RAINER ,  FISCHER WIELAND ,  SEIFERT JEAN-PIERRE

IPC: G06F17/10 ,  G06F7/38 ,  G06F7/72 ,  H04L9/28