公开(公告)号：DE19947082B4

公开(公告)日：2005-02-10

申请号：DE19947082

申请日：1999-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  WILLER JOSEF ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L21/02 ,  H01L27/108

Abstract: A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).

公开(公告)号：DE10104742B4

公开(公告)日：2006-01-12

申请号：DE10104742

申请日：2001-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  SCHUMANN DIRK ,  LUETZEN JOERN

IPC: H01L21/762 ,  H01L21/8242

公开(公告)号：DE10114778A1

公开(公告)日：2002-10-17

申请号：DE10114778

申请日：2001-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAPPELLANI ANNALISA ,  DITTMAR LUDWIG ,  SCHUMANN DIRK

IPC: H01L21/3065 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/78

Abstract: A gate layer stack formed with at least two layers is firstly patterned anisotropically and then thelower layer is etched. An isotropic, preferably selective etching step effects a lateral undercutting, i.e. removal of the lower layer as far as the predetermined channel length to form a dimensionally accurate T-gate transistor with a very short channel length.

公开(公告)号：DE10109564A1

公开(公告)日：2002-09-12

申请号：DE10109564

申请日：2001-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L27/12 ,  H01L27/108

Abstract: The invention relates to a trench condenser for use in a DRAM memory cell and a method for production of said trench condenser. Said trench condenser comprises a lower condenser electrode (10), a memory dielectric (12) and an upper condenser electrode (18), at least partly arranged in a trench (5), whereby the lower condenser electrode (10) lies adjacent to a wall of the trench in the lower region of the trench, whilst in the upper region of the trench, a spacer layer (9), made from an insulating material, is provided adjacent to the wall of the trench. The upper electrode (18) comprises at least two layers (13, 14, 15), of which at least one is metallic, with the proviso that the upper electrode does not comprise two layers of which the lower is tungsten silicide and the upper doped polymeric silicon, whereby the layers (13, 14, 15) of the upper electrode run along the walls and the floor of the trench (5) at least as far as the upper edge of the spacer layer.

公开(公告)号：DE10104742A1

公开(公告)日：2002-08-22

申请号：DE10104742

申请日：2001-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  SCHUMANN DIRK ,  LUETZEN JOERN

IPC: H01L21/762 ,  H01L21/8242

Abstract: A trench structure has an insulating region (60) with a small dielectric constant compared with silicon dioxide. The space taken up by the insulating region is reduced. Preferred Features: The insulating region is partially formed in the edge region (30a, 30b), especially in the wall (32a, 32b) of the trench structure.

公开(公告)号：DE19947082A1

公开(公告)日：2001-04-19

申请号：DE19947082

申请日：1999-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  WILLER JOSEF ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L21/02 ,  H01L27/108

Abstract: The integrated circuit device has at least one capacitor formed in the surface of a semiconductor substrate (1), with one capacitor electrode having a lower part (T) and a side part (S) with 2 opposing side surfaces spaced by less than the height of the side part. At least one side surface of the side part is corrugated with the peaks and troughs extending along lines parallel to the substrate surface, a dielectric layer (KD) applied to the lower part and the side part and a second capacitor electrode (P) applied to the dielectric layer.

公开(公告)号：DE19942680A1

公开(公告)日：2001-04-05

申请号：DE19942680

申请日：1999-09-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  WILLER JOSEF ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L21/02 ,  H01L27/108

Abstract: The capacitor is arranged on the surface of a substrate (1). A first capacitor electrode has a middle part (M) and a side part (ST),which point vertically upwards, are arranged beside each other and are connected with each other via an upper part (O) located above said middle part (M) and said side part (ST). The middle part (M) is longer than the side part (ST) and is connected with other components of the circuit arrangement located below said middle part (M) and said side part (ST). The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) borders the capacitor dielectric (KD).

公开(公告)号：DE19940758A1

公开(公告)日：2001-03-15

申请号：DE19940758

申请日：1999-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAPPELLANI ANNALISA ,  LUSTIG BERNHARD ,  EIBEL NORBERT ,  SCHUMANN DIRK

IPC: H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: The invention relates to a method for producing an HF-FET. According to said method, doped source and drain regions (7, 8) are created in a substrate (1). A gate-insulation layer (4) is applied via a channel region. A spacer structure (6) is created above the substrate (1) which separates the channel region from the source and drain regions. A continuous metal layer (10) is deposited using this structure and the thickness of the metal layer is reduced to such an extent that electrically separate self-aligned metal structures (10.2, 10.3, 10.1) are formed above the source, drain and channel regions.