公开(公告)号：WO03005561A3

公开(公告)日：2003-05-30

申请号：PCT/DE0202408

申请日：2002-07-02

Applicant: INFINEON TECHNOLOGIES AG ,  KLEIN PETER ,  LUSTIG BERNHARD ,  SEWALD DIETER

Inventor： KLEIN PETER ,  LUSTIG BERNHARD ,  SEWALD DIETER

IPC: H03F3/45 ,  H03D7/14

CPC classification number: H03F3/45677 ,  H03F2200/372 ,  H03F2203/45028 ,  H03F2203/45298 ,  H03F2203/45418 ,  H03F2203/45424

Abstract: The invention relates to an interface circuit for connecting to an output of a frequency converter. Said circuit contains at least two current paths (10, 20), which are intercoupled in a parallel connection and respectively comprise at least one cascode stage (12, 13, 22, 23) for signal processing. Said circuit permits direct current offsets of the frequency converter to be compensated, in addition to a switchable amplification ratio for signals with a wide dynamic range and provides a large signal-to-noise margin. The inventive interface circuit is preferably for use in mobile radio telephone receivers.

Abstract translation: 本发明提供一种接口电路，用于连接到频率转换器的输出，是在所述至少两个电流路径（10，20）被提供，其被耦合以并联电路与彼此和在每种情况下为至少一个共源共栅级（12，13，22，23） 包括信号处理。 所描述的电路允许变频器的DC偏移的补偿，以及具有大动态范围的可切换放大比率信号和具有总共大信噪比。 所描述的接口电路是优选适用于移动接收器。

公开(公告)号：DE59705585D1

公开(公告)日：2002-01-10

申请号：DE59705585

申请日：1997-09-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUSTIG BERNHARD ,  SCHAEFER HERBERT ,  FRANOSCH MARTIN

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

Abstract: PCT No. PCT/DE97/01933 Sec. 371 Date Jun. 4, 1999 Sec. 102(e) Date Jun. 4, 1999 PCT Filed Sep. 3, 1996 PCT Pub. No. WO98/13865 PCT Pub. Date Apr. 2, 1998In order to produce a MOS transistor with HDD profile and LDD profile, the HDD profile is firstly formed, followed by the LDD profile, in the area for the LDD profile in order to produce steep dopant profiles. The LDD profile is preferably produced by etching and in situ doped selective epitaxy.

公开(公告)号：DE59607432D1

公开(公告)日：2001-09-06

申请号：DE59607432

申请日：1996-11-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUSTIG BERNHARD

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A MOS transistor has a gate electrode (33) having a T-shaped cross-section. The gate length is defined in a first structuring step by a spacer technique. The area of the gate electrode in the upper region is defined in a second structuring step. The MOS transistor can be produced with a channel length of less than 100 nm.

公开(公告)号：DE50203018D1

公开(公告)日：2005-06-09

申请号：DE50203018

申请日：2002-07-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLEIN PETER ,  LUSTIG BERNHARD ,  SEWALD DIETER

IPC: H03D7/14 ,  H03F3/45

Abstract: In an interface circuit for connection to an output of a frequency converter, at least two current paths are coupled to one another in parallel. Each current path includes at least one cascode stage for signal processing. The circuit compensates for DC voltage offsets of the frequency converter, and has a gain ratio that can be changed over for signals with a large dynamic range.

公开(公告)号：DE10132803A1

公开(公告)日：2002-12-12

申请号：DE10132803

申请日：2001-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUSTIG BERNHARD ,  KLEIN PETER ,  SEWALD DIETER

IPC: H03D7/14 ,  H03F3/45 ,  H03F1/22

Abstract: The interface circuit has a signal input, a signal output, a first current path (10) that couples the signal input to the signal output and contains at least one cascode stage (12,13), a second current path (20) with a cascode stage (22,23) connected in parallel to the first cascode stage and a connection for providing a common mode signal (28) in the first or second current path.

公开(公告)号：DE19940362A1

公开(公告)日：2001-04-12

申请号：DE19940362

申请日：1999-08-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUSTIG BERNHARD ,  SCHAEFER HERBERT ,  RISCH LOTHAR

IPC: H01L29/78 ,  H01L21/335 ,  H01L21/74 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/336

Abstract: Metal oxide semiconductor transistor comprises: sink doped with a first conductivity type in semiconductor substrate; epitaxial layer arranged in sink surface and having doping concentration of less than 10 cm ; and source/drain regions of second conductivity type and a channel region arranged in epitaxial layer. Depth of source/drain regions is less than or equal to epitaxial layer thickness. An Independent claim is also included for a process for the production of the metal oxide semiconductor (MOS) transistor comprising: producing a sink doped with a first conductivity type in the semiconductor substrate; growing an epitaxial layer on the surface of the sink; producing a gate dielectric on the surface of the epitaxial layer; forming a gate electrode on the surface of the gate dielectric; and producing source/drain regions doped with second conductivity type in the epitaxial layer.

公开(公告)号：DE19940758A1

公开(公告)日：2001-03-15

申请号：DE19940758

申请日：1999-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAPPELLANI ANNALISA ,  LUSTIG BERNHARD ,  EIBEL NORBERT ,  SCHUMANN DIRK

IPC: H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: The invention relates to a method for producing an HF-FET. According to said method, doped source and drain regions (7, 8) are created in a substrate (1). A gate-insulation layer (4) is applied via a channel region. A spacer structure (6) is created above the substrate (1) which separates the channel region from the source and drain regions. A continuous metal layer (10) is deposited using this structure and the thickness of the metal layer is reduced to such an extent that electrically separate self-aligned metal structures (10.2, 10.3, 10.1) are formed above the source, drain and channel regions.