公开(公告)号：DE102004023805B4

公开(公告)日：2007-03-08

申请号：DE102004023805

申请日：2004-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN ULRICH ,  SEIDL HARALD

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/334 ,  H01L27/08 ,  H01L29/94

Abstract: The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The fabrication method has the following steps of: providing a semiconductor substrate ( 1; 1', 60, 1 '') having a front side (VS) and a rear side (RS); providing trenches ( 5 ) in the semiconductor substrate ( 1; 1', 60, 1 '') proceeding from the front side (VS) of the semiconductor substrate ( 1; 1', 60, 1 ''); providing a respective inner capacitor electrode ( 6 ) in the trenches ( 5 ); uncovering the inner capacitor electrodes ( 6 ) proceeding from the rear side (RS) of the semiconductor substrate ( 1; 1', 60, 1 ''); providing a capacitor dielectric ( 40 ) on the uncovered inner capacitor electrodes ( 6 ); and providing outer capacitor electrodes ( 50 ) on the capacitor dielectric ( 40 ) on the inner capacitor electrodes ( 6 ).

公开(公告)号：DE102004040943A1

公开(公告)日：2006-03-02

申请号：DE102004040943

申请日：2004-08-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/336

Abstract: For the selective deposition of a layer (4) of HfO 2 or Al 2O 3 on the surface (OF) of a silicon semiconductor substrate (1), using atomic layer deposition (ALD), the surface zones (2,3) are prepared differently using a photo varnish mask. In the first zone (2), the layer is deposited on a layer (6) of SiO 2 by ALD in a 4-20 cycles and preferably 10 cycles. The second zone (3) carries islands (5) of coating material.

公开(公告)号：DE102004040047B3

公开(公告)日：2006-02-16

申请号：DE102004040047

申请日：2004-08-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ULRICH

IPC: H01L21/8242

Abstract: In a process to make a capacitor with first (12) and second (18) capacitor dielectric layers are heat treated and selectively oxidised. The heat treatment and oxidation form a third layer (13) between the two first layers (12, 18).

公开(公告)号：DE102004031111A1

公开(公告)日：2006-01-19

申请号：DE102004031111

申请日：2004-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD

IPC: G03F7/00 ,  G03F7/16 ,  H01L21/308 ,  H01L21/336

Abstract: The method involves structuring an etch resistant layer in such a manner that an allowed area of a hard mask layer (104) lies open. The hard mask layer and a conducting layer (103) are etched underneath an open area of the etch resistant layer. The etch resistant layer and the hard mask layer are removed, and eventually an isotopic etching is provided in such a manner that a sub lithographic conducting layer (103a) is obtained. An independent claim is also included for: a FET with a sub lithographic gate-structure.

公开(公告)号：DE102004019090A1

公开(公告)日：2005-11-24

申请号：DE102004019090

申请日：2004-04-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD

IPC: H01L21/822 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/108

Abstract: Trench capacitor comprises a trench (2) formed in a semiconductor substrate (1), an insulating collar (5'') in the upper region of the trench, a lower metallic capacitor electrode (100'') arranged in the trench on the substrate, an upper conducting capacitor electrode (100''') arranged in the trench and a dielectric layer (70) as capacitor dielectric arranged between the first and second capacitor electrode. The lower capacitor electrode has a stoichiometric composition varying from the substrate to the dielectric layer from a first value (C1) to a second value (C2). An independent claim is also included for: a process for the production of a trench capacitor.

公开(公告)号：DE102004021399B3

公开(公告)日：2005-10-20

申请号：DE102004021399

申请日：2004-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ULRICH

IPC: H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/108

Abstract: The present invention provides a method for fabricating a stacked capacitor array ( 1 ), which comprises a regular arrangement of a plurality of stacked capacitors ( 2 ), with a stacked capacitor ( 2 ) being at a shorter distance from the respective adjacent stacked capacitor ( 2 ) in certain first directions ( 3 ) than in certain second directions ( 4 ), comprising the following method steps: provision of an auxiliary layer stack ( 5 ) having first auxiliary layers ( 6 ) with a predetermined etching rate and at least one second auxiliary layer ( 7 ) with a higher etching rate on a substrate ( 8 ); etching of in each case one hollow cylinder ( 9 ) for each stacked capacitor ( 2 ) through the auxiliary layer stack ( 5 ) in accordance with the regular arrangement, with the auxiliary layer stack ( 5 ) being left in place in intermediate regions ( 10 ) between the hollow cylinders ( 9 ); isotropic etching of the second auxiliary layers ( 7 ) to form widened portions ( 11 ) of the hollow cylinders ( 9 ), without any second auxiliary layer ( 7 ) being left in place between in each case two hollow cylinders ( 9 ) which adjoin one another in the first direction ( 3 ) and with a second residual auxiliary layer ( 7 a) being left in place between in each case two hollow cylinders ( 9 ) which adjoin one another in the second direction ( 4 ); conformal deposition of an insulator layer ( 12 ) in order to completely fill the widened portions ( 11 ); deposition of a first electrode layer ( 13 ) in the hollow cylinders ( 9 ) in order to form the stacked capacitors ( 2 ); filling of the hollow cylinders ( 9 ) with a first filling ( 14 ); removal of the first auxiliary layers ( 6 ), the second residual auxiliary layers ( 7 a) and the first filling ( 14 ) and completion of the stacked capacitor array ( 1 ).

公开(公告)号：DE102004012855A1

公开(公告)日：2005-10-13

申请号：DE102004012855

申请日：2004-03-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: The present invention provides a trench capacitor, in particular for use in a semiconductor memory cell, having a trench ( 5 ) formed in a semiconductor substrate ( 1 ); an insulation collar ( 3 ) in the upper region of the trench ( 5 ); a first conductive capacitor electrode ( 1 a) situated in the trench ( 5 ) or in the semiconductor substrate ( 1 ); a conductive second capacitor electrode ( 10, 25, 30 ), situated in the trench ( 5 ), has a lower nonmetallic part ( 10 ) and an upper metallic part ( 30 ), the upper metallic part ( 30 ) extending right into the region between the insulation collar ( 3 ); a dielectric layer ( 4 ) as capacitor dielectric situated between the first and second capacitor electrodes ( 1 a; 10, 25, 30 ). A part ( 25 ) made of a metal silicide is situated between the lower nonmetallic part ( 10 ) and the upper metallic part ( 30 ). The invention likewise provides a corresponding fabrication method.

公开(公告)号：DE10128718B4

公开(公告)日：2005-10-06

申请号：DE10128718

申请日：2001-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  ALSMEIER JOHANN

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory cell has a selection transistor and a trench capacitor. An upper capacitor electrode of the trench capacitor, in the region of an insulating collar, has a metallic section, and that section of the upper electrode that makes contact with a storage dielectric is of a non-metallic form, in particular containing polysilicon. A buried strap, which connects the upper electrode to the select transistor, is of a non-metallic form, in particular formed of polysilicon.

公开(公告)号：DE10321466A1

公开(公告)日：2004-12-16

申请号：DE10321466

申请日：2003-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  MANGER DIRK ,  GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  SLESAZECK STEFAN

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a "buried" collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.

公开(公告)号：DE10243380A1

公开(公告)日：2004-04-01

申请号：DE10243380

申请日：2002-09-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  MOLL PETER ,  SCHUMANN DIRK ,  SEIDL HARALD

IPC: H01L20060101 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108