公开(公告)号：DE10321466B4

公开(公告)日：2007-01-25

申请号：DE10321466

申请日：2003-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  MANGER DIRK ,  GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  SLESAZECK STEFAN

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/94

Abstract: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a "buried" collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.

公开(公告)号：DE10352667B4

公开(公告)日：2006-10-19

申请号：DE10352667

申请日：2003-11-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SESTERHENN MICHAEL ,  SLESAZECK STEFAN

IPC: H01L21/8242 ,  H01L21/334 ,  H01L27/108

公开(公告)号：DE10352667A1

公开(公告)日：2005-06-16

申请号：DE10352667

申请日：2003-11-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SESTERHENN MICHAEL ,  SLESAZECK STEFAN

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: Production of a semiconductor structure comprises forming a first barrier layer (40) in a lower trench region (2') in a trench (2) in a substrate (1) and filling with a first filler (30), forming a second barrier layer (41) in an upper trench region (2'') and filling with a second filler, removing the second filler in a vertical partial trench and removing the second barrier layer in a base region (21'), changing the properties of a partial region of the first filler to form a third barrier layer (42) below the base region, growing the substrate in the vertical partial trench, removing the second filler and the second barrier layer, removing the upper partial region of the first barrier layer, forming a hole with a fourth barrier layer (43), filling the hole with a hole filler (60) to form a strip, optionally deepening the vertical partial trench by removing the first filler, forming a vertical partial trench with a fifth barrier layer (44), and filling the partial trench with a third filler (32) so that the band forms a conducting trenched contact.

公开(公告)号：DE10318625A1

公开(公告)日：2004-11-25

申请号：DE10318625

申请日：2003-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  SLESAZECK STEFAN

IPC: G11C8/02 ,  H01L21/8242 ,  H01L27/108

Abstract: Memory cell comprises a storage capacitor formed in a trench inserted into a semiconductor substrate (13) away from the substrate surface (14), a transistor (6) arranged between the substrate surface and an upper edge of an inner electrode (4), a source/drain region connected to the inner electrode, and a gate electrode (8). An auxiliary structure (15) is formed in active regions (10) and an addressing line (11) is formed in the region between the substrate surface and the upper edge of the auxiliary structure. An independent claim is also included for a process for the production of the memory cell.

公开(公告)号：DE102005046133A1

公开(公告)日：2006-10-26

申请号：DE102005046133

申请日：2005-09-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SLESAZECK STEFAN ,  SIECK ALEXANDER

IPC: H01L21/336 ,  H01L29/78

Abstract: The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.

公开(公告)号：DE10318625B4

公开(公告)日：2006-08-03

申请号：DE10318625

申请日：2003-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  SLESAZECK STEFAN

IPC: H01L27/108 ,  G11C8/02 ,  H01L21/8242

公开(公告)号：DE10321466A1

公开(公告)日：2004-12-16

申请号：DE10321466

申请日：2003-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  MANGER DIRK ,  GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  SLESAZECK STEFAN

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a "buried" collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.