公开(公告)号：EP0789867A4

公开(公告)日：1999-10-27

申请号：EP95937703

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： KNOLL SHAUN ,  MORRISS JEFF CHARLES ,  CALLAHAN SHELAGH ,  BHATT AJAY V ,  CADAMBI SUDARSHAN BALA

IPC: G06F12/06 ,  G06F13/38 ,  H04L12/40 ,  H04L12/64 ,  G06F3/00 ,  G06F13/00

CPC classification number: H04L12/40058 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/385 ,  H04L12/40078

Abstract: Circuitry and complementary logic are provided to a bus controller (14), a number of 1:n bus signal distributor (18), and a number of bus interfaces (22) of a hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support a hierarchical view of the serial bus elements (16), logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e. the system unit and the interconnected peripheral, as well as assignment of addresses to the serial bus elements and the functions, at power on, reset, and during operation when serial bus elements are hot attached to or detached from the serial bus assembly.

公开(公告)号：EP0789879A4

公开(公告)日：2002-05-02

申请号：EP95939029

申请日：1995-10-30

Applicant: INTEL CORP

Inventor： KNOLL SHAUN ,  MORRISS JEFF CHARLES ,  BHATT AJAY V ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/10 ,  G06F13/22 ,  G06F13/40 ,  H04L12/40 ,  H04L12/64 ,  G06F13/12 ,  G06F13/366 ,  H04L12/44

CPC classification number: H04L12/40058 ,  G06F13/10 ,  G06F13/22 ,  G06F13/4022 ,  H04L12/40065

Abstract: Circuitry and complementary logic are provided to a bus controller (14), a number of 1:n bus signal distributors (18a-18b), and a number of bus interfaces (22a-22f) of an hierarchical serial bus assembly (26') for the bus controller (14) to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents (16a-16f) connected to the serial bus assembly (26') and the serial bus elements themselves. The hierarchical serial bus assembly (26') is used to serially interface a number of isochronous (16a, 16d-16f) and asynchronous (16b-16c) peripherals to the system unit of a computer system. The circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller (14). The circuitry and logic provided in accordance to these gathered critical operating characteristics guarantee latencies and bandwidths to the isochronous functions of the isochronous (16a, 16d-16f) peripherals. In certain embodiments, the circuitry and logic provided to the bus controller (14) further adapt in real time its frame based polling schedule in like manner, responsive to live attachment/detachment of serial bus elements.

公开(公告)号：EP0789872A4

公开(公告)日：1999-10-27

申请号：EP95939039

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： KNOLL SHAUN ,  MORRISS JEFF CHARLES ,  CALLAHAN SHELAGH ,  BHATT AJAY V ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M

IPC: G06F13/38 ,  G06F13/00 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64 ,  G06F9/02

CPC classification number: H04L12/40058 ,  G06F13/423 ,  H04L12/40078

Abstract: A bus controller (14), a number of 1:n bus signal distributors (18), and a number of bus interfaces (22) are provided to form a hierarchical serial bus assembly (26) for serially interfacing a number of isochronous and asynchronous peripherals (16) to the system unit of a computer system. The bus controller (14), bus signal distributors (18), and bus interfaces (22) are provided with circuitry and complementary logic (16c) for implementing a master/slave model of low control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic (16c) further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

公开(公告)号：EP2241068A4

公开(公告)日：2011-10-05

申请号：EP08868735

申请日：2008-11-25

Applicant: INTEL CORP

Inventor： CHANDRA PRASHANT R ,  BHATT AJAY V

IPC: G06F13/38 ,  H04L12/00

CPC classification number: G06F13/387

公开(公告)号：EP2316204A4

公开(公告)日：2011-09-21

申请号：EP09808593

申请日：2009-08-05

Applicant: INTEL CORP

Inventor： CHANDRA PRASHANT R ,  BHATT AJAY V ,  KAHN KEVIN ,  MCGOWAN STEVE

IPC: H04L12/56

CPC classification number: G06F13/122 ,  H04L45/62 ,  H04L47/2491 ,  H04Q11/0062 ,  H04Q11/0066

公开(公告)号：DE112016004883T5

公开(公告)日：2018-08-16

申请号：DE112016004883

申请日：2016-07-08

Applicant: INTEL CORP

Inventor： KUMAR ARVIND ,  BHATT AJAY V ,  VEMBU BALAJI ,  RAMADOSS MURALI ,  CHENG ANTONIO S ,  VALAVI JOHN J ,  GANDRA CHAITANYA R

IPC: G06F3/0488 ,  G06F3/0354

Abstract: Eine Vorrichtung zum schnellen Einfärben einer Berührungsanzeige wird hier beschrieben. Das System zum schnellen Einfärben einer Berührungsanzeige kann das Empfangen einer Berührungseingabe und das Generieren von Berührungssensordaten umfassen. Das System kann eine Grafikverarbeitungseinheit (Graphics Processing Unit, GPU) mit einem Schnelleinfärber und einer Anzeigepipeline aufweisen. Die GPU kann anhand der Berührungssensordaten generierte Daten einer Benutzerschnittstellenvorrichtung (Human Interface Device, HID) an einen Schreibanwendungsspeicher und den Schnelleinfärber übertragen. Der Schnelleinfärber kann die HID-Daten in Einfärbungsdaten umwandeln, die über einen direkten Hardwarepfad an die Anzeigepipeline gesendet werden sollen. Der Schreibanwendungsspeicher kann die HID-Daten in Einfärbungsdaten umwandeln, die an die Anzeigepipeline gesendet werden sollen. Das System kann außerdem eine Berührungsanzeige aufweisen, um Pixel anzuzeigen, die gemäß den von der Anzeigepipeline empfangenen Einfärbungsdaten markiert wurden.

公开(公告)号：DE69522595D1

公开(公告)日：2001-10-18

申请号：DE69522595

申请日：1995-01-06

Applicant: INTEL CORP

Inventor： RABE JEFFREY L ,  BHATT AJAY V ,  BOGIN ZOHAR ,  KARDACH JAMES P ,  SHAH NILESH V

IPC: G06F1/32

Abstract: A power consumption controller is described which switches a computer system between a fully operational mode and a responsive blow power mode. The computer system in the responsive low power mode is responsive to a computer network signal of a specified minimum duration.

公开(公告)号：HK1002784A1

公开(公告)日：1998-09-18

申请号：HK98101350

申请日：1998-02-20

Applicant: INTEL CORP

Inventor： KNOLL SHAUN ,  MORRISS JEFF CHARLES ,  BHATT AJAY V ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/10 ,  G06F13/22 ,  G06F13/40 ,  H04L12/40 ,  H04L12/64 ,  G06F ,  H04L

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals. In certain embodiments, the circuitry and logic provided to the bus controller further adapts in real time its frame based polling schedule in like manner, responsive to live attachment/detachment of serial bus elements.

公开(公告)号：HK1002781A1

公开(公告)日：1998-09-18

申请号：HK98101346

申请日：1998-02-20

Applicant: INTEL CORP

Inventor： KNOLL SHAUN ,  MORRISS JEFF CHARLES ,  CALLAHAN SHELAGH ,  BHATT AJAY V ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M

IPC: G06F20060101 ,  G06F13/38 ,  G06F13/00 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

公开(公告)号：GB2308533A

公开(公告)日：1997-06-25

申请号：GB9707611

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： MORRISS JEFF CHARLES ,  KNOLL SHAUN ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  BHATT AJAY V ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/00 ,  G06F13/36 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: Logic is provided for a bus controller (14), a number of 1:n bus signal distributors (18), and a number of bus interfaces (22) of a hierarchical bus assembly (26) for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly (26). The hierarchical bus assembly (26) is used to serially interface a number of isochronous and asynchronous peripherals (16c-f) to the system unit (12) of a computer system (10). These serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance with the transaction protocols. In some embodiments, these serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.