公开(公告)号：WO2006108169A3

公开(公告)日：2007-04-12

申请号：PCT/US2006013263

申请日：2006-04-05

Applicant: INTEL CORP ,  WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

Inventor： WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

IPC: G06F9/38 ,  G06F9/46

CPC classification number: G06F9/485 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/461 ,  G06F9/4881

Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Abstract translation: 公开了用于在多序列器多线程系统中的逻辑定序器地址与物理或逻辑定序器之间的映射的管理和转换的系统，方法和机制的实施例。 映射管理器可以管理逻辑定序器地址或页面到系统的实际定序器或帧的分配和映射。 与映射管理器相关联的配给逻辑可以在执行这种映射时考虑定序器属性。当重新映射实际的定序器时，与映射管理器相关联的重定位逻辑可以管理向/从备份存储器的上下文信息的溢出和填充。 排序器可以单独分配，或者可以被分配为分区块的一部分。 映射管理器还可以包括每当在用户程序中使用逻辑定序器地址时为映射的定序器提供标识符的翻译逻辑。 还描述和要求保护其他实施例。

公开(公告)号：WO0242902A2

公开(公告)日：2002-05-30

申请号：PCT/US0151023

申请日：2001-10-18

Applicant: INTEL CORP ,  CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

Inventor： CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

IPC: G06F9/38 ,  G06F9/00

CPC classification number: G06F9/3842 ,  G06F9/3861

Abstract: Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is couple to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

Abstract translation: 使用重放队列在处理器中重新安排多个微操作。 处理器包括用于接收多个指令的重放队列和执行多个指令的执行单元。 调度器耦合在重播队列和执行单元之间。 调度器推测性地安排执行指令并将每个指令分派到执行单元。 检查器耦合到执行单元，以确定每个指令是否已成功执行。 检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

公开(公告)号：WO2006074024A3

公开(公告)日：2006-10-26

申请号：PCT/US2005047328

申请日：2005-12-28

Applicant: INTEL CORP ,  WANG HONG ,  SHEN JOHN ,  GROCHOWSKI ED ,  HELD JAMES PAUL ,  BIGBEE BRYANT ,  KAUSHIK SHIVNANDAN D ,  CHINYA GAUTHAM ,  ZOU XIANG ,  HAMMARLUND PER ,  TIEN XINMIN ,  AGGARWAL ANIL ,  RODGERS SCOTT DION ,  PATEL BAIJU V ,  HANKINS RICHARD

Inventor： WANG HONG ,  SHEN JOHN ,  GROCHOWSKI ED ,  HELD JAMES PAUL ,  BIGBEE BRYANT ,  KAUSHIK SHIVNANDAN D ,  CHINYA GAUTHAM ,  ZOU XIANG ,  HAMMARLUND PER ,  TIEN XINMIN ,  AGGARWAL ANIL ,  RODGERS SCOTT DION ,  PATEL BAIJU V ,  HANKINS RICHARD

IPC: G06F9/48

CPC classification number: G06F9/3851 ,  G06F9/4843

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Abstract translation: 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。

公开(公告)号：WO2005013121A3

公开(公告)日：2005-11-17

申请号：PCT/US2004023570

申请日：2004-07-21

Applicant: INTEL CORP

Inventor： HAMMARLUND PER ,  CROSSLAND JAMES ,  KAUSHIK SHIVNANDAN ,  AGGARWAL ANIL

IPC: G06F9/46 ,  G06F9/48 ,  G06F15/167 ,  G06F9/54

CPC classification number: G06F9/4812 ,  G06F9/544

Abstract: According to an embodiment of the invention, a method and apparatus for inter-processor interrupts in a multi-processor system are described. An embodiment comprises writing an inter-processor interrupt request to a first memory location; monitoring the first memory location; detecting the inter-processor interrupt request in the first memory location; calling a function for the inter-processor interrupt request; and performing the function for the inter-processor interrupt request.

Abstract translation: 根据本发明的实施例，描述了用于多处理器系统中的处理器间中断的方法和装置。 一个实施例包括将处理器间中断请求写入第一存储器位置; 监控第一个内存位置; 检测第一存储器位置中的处理器间中断请求; 调用处理器间中断请求的功能; 并执行处理器间中断请求的功能。

公开(公告)号：WO0239269A3

公开(公告)日：2003-01-23

申请号：PCT/US0150735

申请日：2001-10-18

Applicant: INTEL CORP ,  CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

Inventor： CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3861

Abstract: Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprise a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled tot he execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

Abstract translation: 使用重新安排的重播队列在处理器中重新播放依赖循环。 处理器包括用于接收多个指令的重播队列，以及执行多个指令的执行单元。 调度器耦合在重播队列和执行单元之间。 调度器推测性地调度用于执行的指令，并且为多个指令中的每一个递增计数器，以反映多个指令中的每一个已被执行的次数。 当计数器不超过最大重放次数时，或者当计数器超过最大重放次数时，当指令执行安全时，调度器也将每条指令分派给执行单元。 检查器与执行单元相连以确定每个指令是否已成功执行。 检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

公开(公告)号：EP3123343A4

公开(公告)日：2017-11-22

申请号：EP14887397

申请日：2014-03-24

Applicant: INTEL CORP

Inventor： LOH THIAM WAH ,  CHINYA GAUTHAM N ,  HAMMARLUND PER ,  FORTAS REZA ,  WANG HONG ,  SUN HUAJIN

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F2213/2404 ,  G06F2213/2406 ,  Y02D10/14

Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

公开(公告)号：RU2651238C2

公开(公告)日：2018-04-18

申请号：RU2016134601

申请日：2014-03-24

Applicant: INTEL CORP

Inventor： LOH THIAM WAH ,  CHINYA GAUTHAM N ,  HAMMARLUND PER ,  FORTAS REZA ,  WANG HONG ,  SUN HUAJIN

IPC: G06F13/24 ,  G06F9/48

Abstract: Группаизобретенийотноситсяк областивычислительнойтехникии можетбытьиспользованадляобработкипрерываний. Техническимрезультатомявляетсяуменьшениепотребленияэнергиипроцессором. Процессорсодержит, поменьшеймере, одноядро, включаяв себяпервоеядро; илогикузадержкипрерывания, предназначеннуюдля: приемапервогопрерыванияв первоевремя; задержкинапервоевремязадержки, котороеначинаетсяв первоевремя, обработкипервогопрерыванияпервымядром, втовремякакпервоепрерываниенаходитсяв состоянииожидания, вовтороевремя, когданачинаетсяобработкавторогопрерыванияпервымядром; иеслипервоепрерываниенаходитсяв состоянииожиданиявовтороевремя, обозначениядляпервогоядра, начинатьобработкупервогопрерыванияпередзавершениемпервоговременизадержки, вкоторомвтороепрерываниепринимаютпериодически, идлякаждогопоявлениявторогопринятогопрерываниявтороепрерываниедолжнобытьобработанопервымядромбезпреднамереннойзадержки, илогиказадержкипрерываниядолжнаобозначатьдляпервогоядраначатьобработкудополнительныхпрерыванийв состоянииожиданиядозавершениясоответствующейзадержкии покаядроостаетсяв активномсостоянии. 3 н. и 16 з.п. ф-лы, 8 ил.

公开(公告)号：DE102010052680A1

公开(公告)日：2011-07-07

申请号：DE102010052680

申请日：2010-11-26

Applicant: INTEL CORP

Inventor： DIXON MARTIN G ,  RODGERS SCOTT D ,  BAHRAMI TARANEH ,  GUNTHER STEPHEN H ,  SETHI PRASHANT ,  HAMMARLUND PER

IPC: G06F9/30 ,  G06F1/32

Abstract: Bei einer Ausführungsform umfasst die vorliegende Erfindung einen Prozessor, der einen Kern mit Decodierlogik aufweist, um einen Befehl zu decodieren, der eine Identifizierung einer zu überwachenden Position und einen Zeitgeberwert vorschreibt, und einen mit der Decodierlogik gekoppelten Zeitgeber, um eine Zählung in Bezug auf den Zeitgeberwert auszuführen. Der Prozessor kann weiter eine mit dem Kern gekoppelte Power-Mangement-Einheit umfassen, um eine Art eines Energiesparzustandes basierend mindestens teilweise auf dem Zeitgeberwert zu bestimmen und den Prozessor zu veranlassen, in den Energiesparzustand als Reaktion auf die Bestimmung einzutreten. Weitere Ausführungsformen sind beschrieben und werden beansprucht.

公开(公告)号：GB2441903A

公开(公告)日：2008-03-19

申请号：GB0719770

申请日：2004-06-16

Applicant: INTEL CORP

Inventor： HAMMARLUND PER ,  CROSSLAND JAMES ,  AGGARWAL ANIL ,  KAUSHIK SHIVNANDAN

IPC: G06F9/46 ,  G06F9/50

Abstract: A method of handling locks in a system comprises the steps of creating a queue element (a node) and associating it with a processor waiting for a contended lock. A monitor is then set up to monitor the node and the processor relinquishes its resources and is put into a sleep state. The node is monitored and when an event occurs the processor is exited from the sleep state and resumes control of the previously relinquished resources. Once awake the monitoring of the node is disabled. Relinquished resources may be combined to form larger resources for non-sleeping processors. Relinquishing resources comprises the steps of relinquishing registers and entries in instructions queues, buffers and reorder buffers. An event may comprise a processor reaching its turn in to claim ownership of a lock or the lock becoming available. Initiating the monitor comprises setting up a monitor address associated with the queue element or node.

公开(公告)号：DE112005001515T5

公开(公告)日：2007-05-10

申请号：DE112005001515

申请日：2005-06-17

Applicant: INTEL CORP

Inventor： SAHA BRATIN ,  MERTEN MATTHEW C ,  HAMMARLUND PER

IPC: G06F9/38

Abstract: A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.