公开(公告)号：ES2138051T3

公开(公告)日：2000-01-01

申请号：ES94307771

申请日：1994-10-21

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN

IPC: G06F9/38

Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.

公开(公告)号：DE69420540D1

公开(公告)日：1999-10-14

申请号：DE69420540

申请日：1994-10-21

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38

Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.

公开(公告)号：SG52391A1

公开(公告)日：1998-09-28

申请号：SG1996003892

申请日：1994-10-21

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D´SA REYNOLD V

IPC: G06F9/38

Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.

公开(公告)号：PL307460A1

公开(公告)日：1995-09-04

申请号：PL30746095

申请日：1995-02-27

Applicant: INTEL CORP

Inventor： HINTON GLENN J ,  PAPWORTH DAVID B ,  GLEW ANDREW F ,  FETTERMAN MICHAEL A ,  COLWELL ROBERT P

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G09F13/04

Abstract: A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages. The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results. In one embodiment, the instructions are executed by determining the data readiness of each of the operations and scheduling data ready operations. These scheduled data ready operations are dispatched to an execution unit and executed. The results are written back for use by other operations or as data output or indication. The determination of execution readiness, the dispatching and the execution, and writeback, are performed in consecutive pipestages. The present invention also provides for retiring each of the continuous stream of operations in such a manner as to commit their results to architectural state and to reestablish sequential program order.

公开(公告)号：GB2284493A

公开(公告)日：1995-06-07

申请号：GB9417470

申请日：1994-08-31

Applicant: INTEL CORP

Inventor： PAPWORTH DAVID B ,  HINTON GLEN J ,  FETTERMAN MICHAEL ALAN ,  COLWELL ROBERT P ,  GLEW ANDREW F

IPC: G06F9/38

Abstract: A method and circuitry for coordinating exceptions in a processor in which instructions may be executed "out-of-order", depending on the availability of execution resources; this would generally cause problems when an exception is generated by an instruction which has been executed speculatively, or out-of-order. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to process an exception if one is indicated by any of the exception data values.

公开(公告)号：DE102014003855B4

公开(公告)日：2019-12-19

申请号：DE102014003855

申请日：2014-03-17

Applicant: INTEL CORP

Inventor： MUTHIAH BHARATH ,  RASH WILLIAM BILL ,  HINTON GLENN J ,  DIXON MARTIN G ,  HAHN SCOTT D ,  PAPWORTH DAVID B

IPC: H04N21/2343 ,  G06F9/445 ,  H04N21/2662

Abstract: System (800) mit:einem Server (102, 206), der einen Hauptprozessor und eine Netzwerkschnittstelle aufweist, wobei der Hauptprozessor einen ersten Befehlssatz aufweist, wobei der Server zum Übersetzen einer Binärdatei, die einen zweiten Befehlssatz aufweist, in eine übersetzte ausführbare Datei dient, die den ersten Befehlssatz aufweist, wobei die Übersetzung unter Verwendung von Quality-of-Service(QoS)-Kriterien ausgeführt wird, wobei die QoS-Kriterien eine prioritätsbasierte Beschleunigung und mehrere Client-Parameter einschließen, wobei die mehreren Client-Parameter eine Client-Vorrichtungsauflösung, eine Client-Vorrichtungslage, einen Client-Anwendungstyp und einen Satz von Client-Decodierungsfähigkeiten umfassen, wobei die prioritätsbasierten Beschleunigungsfaktoren eine Netzwerklatenzzeit zwischen dem Server und der Client-Vorrichtung (175, 202) zum Festlegen der Binärübersetzungspriorität umfassen, wobei der Server die übersetzte Binärdatei ausführt, um einen Rahmen einer gerenderten Ausgabe zu erzeugen, und den Rahmen der gerenderten Ausgabe über die Netzwerkschnittstelle überträgt; undeiner Client-Vorrichtung (175, 202), die ein Display, einen Client-Prozessor und eine Client-Netzwerkschnittstelle aufweist, wobei die Client-Vorrichtung von dem Server (102, 206) den Rahmen der gerenderten Ausgabe über die Client-Netzwerkschnittstelle empfängt und den Rahmen der gerenderten Ausgabe auf dem Display unter Verwendung des Client-Prozessors (314, 400, 810, 970, 980) anzeigt, wobei der Server (102, 206) die Binärübersetzung in einer virtuellen Maschine (208) ausführt, wobei die virtuelle Maschine (208) für die Client-Vorrichtung (175, 202) abgestimmt ist, wobei die Ausführungsressourcen der virtuellen Maschine (208) über die QoS-Kriterien abgestimmt sind.

公开(公告)号：GR3036841T3

公开(公告)日：2002-01-31

申请号：GR990403158

申请日：1999-12-07

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38

Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.

公开(公告)号：SG75756A1

公开(公告)日：2000-10-24

申请号：SG1996001617

申请日：1994-08-17

Applicant: INTEL CORP

Inventor： COLWELL ROBERT P ,  HINTON GLENN J ,  MARTELL ROBERT W ,  PAPWORTH DAVID B ,  FETTERMAN MICHAEL ALAN ,  GLEW ANDREW F

IPC: G06F9/38 ,  G06F9/28 ,  G06F9/00 ,  G06F9/26 ,  G06F13/00

公开(公告)号：AU3390900A

公开(公告)日：2000-10-04

申请号：AU3390900

申请日：2000-02-29

Applicant: INTEL CORP

Inventor： SHAHIDZADEH SHAHROKH ,  BIGBEE BRYANT E ,  PAPWORTH DAVID B ,  BINNS FRANK ,  COLWELL ROBERT P

IPC: G06F9/34 ,  G06F9/355 ,  G06F12/02 ,  G06F9/318

Abstract: A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

公开(公告)号：PL178770B1

公开(公告)日：2000-06-30

申请号：PL30746095

申请日：1995-02-27

Applicant: INTEL CORP

Inventor： HINTON GLENN J ,  PAPWORTH DAVID B ,  GLEW ANDREW F ,  FETTERMAN MICHAEL A ,  COLWELL ROBERT P

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G09F13/04 ,  G06F15/76

Abstract: A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages. The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results. In one embodiment, the instructions are executed by determining the data readiness of each of the operations and scheduling data ready operations. These scheduled data ready operations are dispatched to an execution unit and executed. The results are written back for use by other operations or as data output or indication. The determination of execution readiness, the dispatching and the execution, and writeback, are performed in consecutive pipestages. The present invention also provides for retiring each of the continuous stream of operations in such a manner as to commit their results to architectural state and to reestablish sequential program order.