公开(公告)号：GB2511975A

公开(公告)日：2014-09-17

申请号：GB201410920

申请日：2011-12-21

Applicant: INTEL CORP

Inventor： SASTRY MANOJ R ,  SCHOINAS IOANNIS T ,  TOEPFER ROBERT J ,  TRIVEDI ALPA T NARENDRA ,  LONG MEN

IPC: G06F13/14 ,  G06F21/76

Abstract: In one embodiment, the present invention includes a system on a chip (SoC) that has a first agent with an intellectual property (IP) logic, an interface to a fabric including a target interface, a master interface and a sideband interface, and an access control plug-in unit to handle access control policy for the first agent with respect to incoming and outgoing transactions. This access control plug-in unit can be incorporated into the SoC at integration time and without any modification to the IP logic. Other embodiments are described and claimed.

公开(公告)号：GB2470878B

公开(公告)日：2013-03-20

申请号：GB201017257

申请日：2009-03-31

Applicant: INTEL CORP

Inventor： CHERUKURI NAVEEN ,  SCHOINAS IOANNIS T ,  KUMAR AKHILESH ,  PARK SEUNGJOON ,  CHOU CHINGTSUN

IPC: G06F12/08 ,  G06F9/06 ,  H04L45/17 ,  G06F9/46 ,  G06F9/54

Abstract: A method, router node, and set of instructions for using express virtual channels in a component network on a chip are disclosed. An input link 302 may receive an express flow control unit from a source node 102 in a packet-switched network via an express virtual channel 110. An output link 306 may send the express flow control unit to a sink node 106. A switch allocator 322 may forward the express flow control unit directly to the output link 306.

公开(公告)号：DE102005014462B4

公开(公告)日：2013-01-17

申请号：DE102005014462

申请日：2005-03-30

Applicant: INTEL CORP

Inventor： WILSON JOHN H ,  SCHOINAS IOANNIS T ,  YOUSIF MAZIN S ,  RANKIN LINDA J ,  GRAWROCK DAVID W ,  GREINER ROBERT J ,  SUTTON JAMES A ,  VAID KUSHAGRA ,  WISEMAN WILLARD M

IPC: G06F9/445 ,  G06F21/24 ,  G06F1/00 ,  G06F9/46 ,  G06F12/14 ,  G06F15/163 ,  G06F15/177 ,  H04L9/00

Abstract: Verfahren zum Starten eines sicheren Kernels in einem System mit einer teilweise oder einer vollständig verbundenen Topologie, das System eine Mehrzahl von Knoten aufweist und jeder Knoten eine Mehrzahl von Prozessoren enthält; umfassend Laden eines Trusted Agents und eines sicheren Kernels in eine sichere Speichereinrichtung, die in dem System vorgesehen ist, wobei die sichere Speichereinrichtung für jeden der Knoten zugänglich ist, und Initiieren eines sicheren Starts auf einem bestimmten Prozessor, der in einem bestimmten Knoten enthalten ist, Konstruieren eines Spannbaums durch den bestimmten Prozessor, wobei der Spannbaum alle anderen Knoten des Systems in Bezug auf den bestimmten Knoten in einer Mehrzahl von Stufen einer Baumstruktur identifiziert; Senden einer sicheren Startmeldung an den anderen Knoten, der in dem Spannbaum identifiziert ist, durch den bestimmten Prozessor; als Antwort auf die sichere Startmeldung von dem anderen Knoten Validieren des in die sichere Speichereinrichtung geladenen Trusted Agents durch den bestimmten...

公开(公告)号：GB2470878A

公开(公告)日：2010-12-08

申请号：GB201017257

申请日：2009-03-31

Applicant: INTEL CORP

Inventor： CHERUKURI NAVEEN ,  SCHOINAS IOANNIS T ,  KUMAR AKHILESH ,  PARK SEUNGJOON ,  CHOU CHINGTSUN

IPC: G06F12/08 ,  G06F9/06 ,  H04L45/17 ,  G06F9/46

Abstract: A method, chip multiprocessor tile, and a chip multiprocessor with amorphous caching are disclosed. An initial processing core 404 may retrieve a data block from a data storage. An initial amorphous cache bank 410 adjacent to the initial processing. core 404 may store an initial data block copy 422. A home bank directory 424 may register the uitial data block copy 422.

公开(公告)号：GB2433807B

公开(公告)日：2008-10-22

申请号：GB0704417

申请日：2007-03-07

Applicant: INTEL CORP

Inventor： SCHOINAS IOANNIS T ,  MADUKKARUMUKUMANA RAJESH ,  NEIGER GILBERT ,  UHLIG RICHARD ,  VEMBU BALAJI

IPC: G06F12/10 ,  G06F13/20 ,  G06F13/28

Abstract: An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physical address corresponds to a guest domain identified by a guest domain identifier in an input/output (I/O) transaction requested by an I/O device. A register stores an invalidating domain identifier identifying an invalidating domain and an indicator indicating invalidating an entry in the cached entries having a tag.

公开(公告)号：GB2433807A

公开(公告)日：2007-07-04

申请号：GB0704417

申请日：2007-03-07

Applicant: INTEL CORP

Inventor： SCHOINAS IOANNIS T ,  MADUKKARUMUKUMANA RAJESH ,  NEIGER GILBERT ,  UHLIG RICHARD ,  VEMBU BALAJI

IPC: G06F12/10 ,  G06F13/20 ,  G06F13/28

Abstract: An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physical address corresponds to a guest domain identified by a guest domain identifier in an input/output (I/O) transaction requested by an I/O device. A register stores an invalidating domain identifier identifying an invalidating domain and an indicator indicating invalidating an entry in the cached entries having a tag.

公开(公告)号：GB2431757A

公开(公告)日：2007-05-02

申请号：GB0703503

申请日：2005-09-01

Applicant: INTEL CORP

Inventor： SCHOINAS IOANNIS T ,  MADUKKARUMUKUMANA RAJESH ,  NEIGER GILBERT ,  UHLIG RICHARD ,  KING KU-JEI

IPC: G06F12/10 ,  G06F13/38 ,  G06F13/40

Abstract: An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O device. An address translation structure translates the guest physical address to a host physical address corresponding to the I/O transaction.

公开(公告)号：GB2429555A

公开(公告)日：2007-02-28

申请号：GB0620519

申请日：2004-09-23

Applicant: INTEL CORP

Inventor： WILSON JOHN H ,  SCHOINAS IOANNIS T ,  YOUSIF MAZIN S ,  RANKIN LINDA J ,  GRAWROCK DAVID W ,  GREINER ROBERT J ,  SUTTON JAMES A ,  VAID KUSHAGRA ,  WISEMAN WILLARD M

IPC: G06F21/00 ,  G06F21/24 ,  G06F1/00 ,  G06F9/445 ,  G06F9/46 ,  G06F12/14 ,  G06F15/163 ,  G06F15/177 ,  G06F15/80 ,  H04L9/00

Abstract: An initial logical processor is used to construct a spanning tree (300) across a plurality of processors (212), and the spanning tree (300) is used to launch a trusted agent on the processor.