公开(公告)号：US20230096835A1

公开(公告)日：2023-03-30

申请号：US17484519

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kyle McElhinny ,  Bohan Shan ,  Hongxia Feng ,  Xiaoying Guo ,  Adam Schmitt ,  Jacob Vehonsky ,  Steve Cho ,  Leonel Arana

IPC: H01L23/00 ,  H01L21/60 ,  H01L23/538

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.

公开(公告)号：US20230095281A1

公开(公告)日：2023-03-30

申请号：US17484499

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kyle McElhinny ,  Hongxia Feng ,  Xiaoying Guo ,  Steve Cho ,  Jung Kyu Han ,  Changhua Liu ,  Leonel Arana ,  Rahul Manepalli ,  Dingying Xu ,  Amram Eitan

IPC: H01L23/00 ,  H01L21/60 ,  H01L23/488 ,  H01L23/538

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

公开(公告)号：US20250132239A1

公开(公告)日：2025-04-24

申请号：US19005161

申请日：2024-12-30

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Thomas Stanley Heaton ,  Shayan Kaviani ,  Yonggang Li ,  Mahdi Mohammadighaleni ,  Bai Nie ,  Dilan Seneviratne ,  Joshua James Stacey ,  Hiroki Tanaka ,  Elham Tavakoli ,  Ehsan Zamani

IPC: H01L23/498

Abstract: Porous liners for through-glass vias and associated methods are disclosed. An example apparatus includes a glass layer having a through-hole. The example apparatus further includes a conductive material within the through-hole. The example apparatus also includes a porous material between at least a portion of the conductive material and at least a portion of a sidewall of the through-hole.

公开(公告)号：US20250112124A1

公开(公告)日：2025-04-03

申请号：US18374555

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Leonel Arana ,  Gang Duan ,  Benjamin Duong ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon C. Marin ,  Tchefor Ndukum ,  Bai Nie ,  Srinivas Pietambaram ,  Bohan Shan ,  Matthew Tingey

IPC: H01L23/482 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: DEEP CAVITY ARRANGEMENTS ON INTEGRATED CIRCUIT PACKAGING An electronic package, comprises a substrate core; dielectric material of one or more dielectric material layers over the substrate core, and having a plurality of metallization layers comprising an upper-most metallization layer; and an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer. The package also has a metallization pattern within the dielectric material and below the IC die; and a gap within the dielectric material and extending around the metallization pattern.

公开(公告)号：US20250006645A1

公开(公告)日：2025-01-02

申请号：US18343892

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Xiao Liu ,  Bohan Shan ,  Dingying Xu ,  Gang Duan ,  Haobo Chen ,  Hongxia Feng ,  Jung Kyu Han ,  Xiaoying Guo ,  Zhixin Xie ,  Xiyu Hu ,  Robert Alan May ,  Kristof Kuwawi Darmawikarta ,  Changhua Liu ,  Yosuke Kanaoka

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/58 ,  H01L25/10

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (PID) or an organic non-photoimageable dielectric (non-PID); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.

公开(公告)号：US20240243087A1

公开(公告)日：2024-07-18

申请号：US18620569

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Ryan Joseph Carrazzone ,  Anastasia Arrington ,  Haobo Chen ,  Hongxia Feng ,  Catherine Ka-Yan Mau ,  Kyle Matthew McElhinny ,  Dingying Xu

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/1146 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/1357 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2924/384

Abstract: Systems, apparatus, articles of manufacture, and methods to reduce variation in height of bumps after flow are disclosed. An example apparatus includes a substrate of an integrated circuit package, a first bump on the substrate, a second bump on the substrate, and a third bump on the substrate. The first bump includes first solder on a first metal pad. The first metal pad has a first width and a first thickness. The second bump includes second solder on a second metal pad. The second metal pad has a second width and a second thickness. The second width is less than the first width. The second thickness matches the first thickness. The third bump includes third solder on a third metal pad. The third metal pad has a third width. The third width less than the second width.

公开(公告)号：US20240222304A1

公开(公告)日：2024-07-04

申请号：US18148148

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Jiaqi Wu ,  Haobo Chen ,  Srinivas Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/538 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16

Abstract: Methods and apparatus to reduce solder bump bridging between two substrates. An apparatus includes a first substrate including a first bump and a second bump spaced apart from the first bump, the first bump including a first base, the second bump including a second base; and a second substrate including a third bump and a fourth bump spaced apart from the third bump, the third bump including a third base, the fourth bump including a fourth base, the first base electrically coupled to the third base by first solder, the second base electrically coupled to the fourth base by second solder, the first solder having a first volume, the second solder having a second volume, the first volume less than the second volume.

公开(公告)号：US20240222238A1

公开(公告)日：2024-07-04

申请号：US18091543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15

CPC classification number: H01L23/49811 ,  H01L23/15 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/81815

Abstract: An integrated circuit device substrate includes a glass substrate with a first major surface comprising a plateau region, a cavity region, and a wall between the plateau region and the cavity region. The first major surface includes thereon a first dielectric region, and the plateau region includes a plurality of conductive pillars. A second major surface of the glass substrate opposite the first major surface includes thereon a second dielectric layer, wherein the second dielectric layer includes at least one dielectric-free window underlying the cavity region.

公开(公告)号：US20240215269A1

公开(公告)日：2024-06-27

申请号：US18086232

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13023

Abstract: An electronic system includes a substrate that includes a glass core layer including a cavity formed through the glass core layer; at least one active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer and a first surface of the at least one active component die, wherein the first buildup layer includes electrically conductive interconnect contacting the at least one active component die and extending to a first surface of the substrate; a second buildup layer contacting a second surface of the glass core layer and a second surface of the at least one active component die; and one or more solder bumps on a second surface of the substrate and contacting the second surface of the at least one active component die.

公开(公告)号：US20240213116A1

公开(公告)日：2024-06-27

申请号：US18069507

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Dingying Xu ,  Xiaoying Guo ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/538

CPC classification number: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/5383

Abstract: Methods, systems, apparatus, and articles of manufacture to cool integrated circuit packages having glass substrates are disclosed. An example glass core of an integrated circuit (IC) package disclosed herein includes a fluid inlet to receive a cooling fluid, a fluid outlet, and a channel to fluidly couple the fluid inlet to the fluid outlet, the cooling fluid to flow through the channel from the fluid inlet to the fluid outlet, the channel fluidly isolated from one or more vias extending between a first surface and a second surface of the glass core.