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    22.
    发明专利
    未知

    公开(公告)号：NO20065601A

    公开(公告)日：2007-01-31

    申请号：NO20065601

    申请日：2006-12-05

    Applicant: INTERDIGITAL TECH CORP

    Inventor： CASTOR DOUGLAS R ,  LEVI ALAN M ,  DESAI BINISH P

    IPC: H04L12/66 ,  H04B7/00 ,  H04J11/00 ,  H04L12/56 ,  H04W28/14

    CPC classification number: H04L47/14 ,  H04L47/50 ,  H04L47/564 ,  H04L47/621 ,  H04W28/14

    Abstract: A method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor and a memory including at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on the TTI of each data block, such that a data block having a larger TTI is allocated to the memory stack earlier and deallocated from the stack later than a data block having a smaller TTI. In one embodiment, the memory includes a first memory stack for common/shared uplink channels, a second memory stack for dedicated uplink channels, a third memory stack for common/shared downlink channels, and a fourth memory stack for dedicated downlink channels.

    23.
    发明专利
    未知

    公开(公告)号：BR0209086A

    公开(公告)日：2004-08-10

    申请号：BR0209086

    申请日：2002-04-16

    Applicant: INTERDIGITAL TECH CORP

    Inventor： CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  MORABITO JOSEPH T

    IPC: H03M13/23 ,  H03M13/27 ,  H03M13/29 ,  H04B1/69 ,  H04B7/155 ,  H04B7/208 ,  H04B7/212 ,  H04B7/216 ,  H04B7/26 ,  H04J3/00 ,  H04J3/02 ,  H04L1/00 ,  H04Q11/00 ,  H04W88/02 ,  H04W88/08

    Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer. The physical channel buffer addresses are determined corresponding to addresses of the bits after rate matching, bit scrambling, second interleaving and physical channel mapping. The bits are directly read from the first interleaver buffer and written to the physical channel buffer using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer from the address of bits in the physical channel buffer. The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching, reverse bit scrambling, reverse second interleaving and reverse physical channel mapping. The bits are directly read from the determined first interleaver buffer addresses and written to the physical channel buffer addresses.

    30.
    发明专利
    未知

    公开(公告)号：NO20034603L

    公开(公告)日：2003-12-08

    申请号：NO20034603

    申请日：2003-10-14

    Applicant: INTERDIGITAL TECH CORP

    Inventor： CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  MORABITO JOSEPH T

    IPC: H03M13/23 ,  H03M13/27 ,  H03M13/29 ,  H04B1/69 ,  H04B7/155 ,  H04B7/208 ,  H04B7/212 ,  H04B7/216 ,  H04B7/26 ,  H04J3/00 ,  H04J3/02 ,  H04L1/00 ,  H04Q11/00 ,  H04W88/02 ,  H04W88/08

    Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer. The physical channel buffer addresses are determined corresponding to addresses of the bits after rate matching, bit scrambling, second interleaving and physical channel mapping. The bits are directly read from the first interleaver buffer and written to the physical channel buffer using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer from the address of bits in the physical channel buffer. The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching, reverse bit scrambling, reverse second interleaving and reverse physical channel mapping. The bits are directly read from the determined first interleaver buffer addresses and written to the physical channel buffer addresses.

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