HIGH PERFORMANCE WIRELESS RECEIVER WITH CLUSTER MULTIPATH INTERFERENCE SUPPRESSION CIRCUIT
    26.
    发明公开
    HIGH PERFORMANCE WIRELESS RECEIVER WITH CLUSTER MULTIPATH INTERFERENCE SUPPRESSION CIRCUIT 审中-公开
    具有群集更多的途径故障抑制电路WIRELESS高性能接收机

    公开(公告)号:EP1649604A4

    公开(公告)日:2007-01-17

    申请号:EP04778184

    申请日:2004-07-13

    Abstract: A receiver which suppresses inter-cluster multipath interference by processing an impulse channel response consisting of two multipath clusters, each cluster having groups of signals with multiple delays. In one embodiment, the receiver includes a single antenna and parallel-connected delay units used to align the groups of signals before being input into respective sliding window equalizers. The outputs of the equalizers are combined at chip level via a combiner which provides a single output. In another embodiment, a Cluster Multipath Interference Suppression (CMIS) circuit is incorporated into the receiver. The CMIS circuit includes a hard decision unit and a plurality of signal regeneration units to generate replicas of the multipath clusters. The replicas are subtracted from the respective outputs of the delay units and the results are input to the respective sliding window equalizers. In another embodiment, multiple antennas are used to receive and process the clusters.

    METHOD AND SYSTEM FOR ALL DIGITAL GAIN CONTROL
    28.
    发明公开
    METHOD AND SYSTEM FOR ALL DIGITAL GAIN CONTROL 有权
    VERFAHREN UND系统FÜRDURCHWEG DIGITALEVERSTÄRKUNGSREGELUNG

    公开(公告)号:EP1512237A4

    公开(公告)日:2005-11-30

    申请号:EP03734444

    申请日:2003-06-05

    CPC classification number: H03G7/06 H03G3/001 H03M1/1235

    Abstract: An analog/digital gain control device avoid some of the requirements associated with the nature of a closed-loop AGC circuits and which meets the remaining requirements without much difficulty uses an analog to digital conversion method that increases the number of effective ADC bits by compressing the baseband input analog signal using a logarithmic circuit. After the compressed analog signal is converted into a digital signal, a digital anti-log process or look-up table (LUT) is used to expand the digital signal back to the original linear scale. The word size of the output of the anti-log process is larger than the input word size due to the nature of the anti-log function. To reduce the word size of the digital signal an open loop normalization technique can be applied.

    Abstract translation: 模拟/数字增益控制设备避免了一些与闭环AGC电路性质相关的要求,并且能够毫不费力地满足其余要求,使用模数转换方法,通过压缩该模数转换方法来增加有效ADC位数 基带输入模拟信号采用对数电路。 在将压缩的模拟信号转换为数字信号之后,使用数字反对数处理或查找表(LUT)将数字信号扩展回原始线性比例。 由于反对数函数的性质,反对数进程输出的字大小大于输入字大小。 为了减小数字信号的字长,可以应用开环标准化技术。

    METHOD AND APPARATUS FOR ESTIMATING AND CORRECTING BASEBAND FREQUENCY ERROR IN A RECEIVER
    30.
    发明公开
    METHOD AND APPARATUS FOR ESTIMATING AND CORRECTING BASEBAND FREQUENCY ERROR IN A RECEIVER 审中-公开
    方法和装置在接收机中估计和校正的基带频率误差

    公开(公告)号:EP1815601A4

    公开(公告)日:2008-01-23

    申请号:EP05813289

    申请日:2005-10-19

    CPC classification number: H04B1/7097 H04B1/712 H04L25/03248

    Abstract: A method and apparatus for estimating and correcting baseband frequency error in a receiver. In one embodiment, an equalizer performs equalization on a sample data stream and generates filter tap values based on the equalization. An estimated frequency error signal is generated based on at least one of the filter tap values. A rotating phasor is generated based on the estimated frequency error signal. The rotating phasor signal is multiplied with the sample data stream to correct the frequency of the sample data stream. In another embodiment, a channel estimator performs channel estimation and generates Rake receiver finger weights based on at least one of the finger weights. An estimated frequency error signal is generated based on at least one of the finger weights.

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