公开(公告)号：WO2016036572A2

公开(公告)日：2016-03-10

申请号：PCT/US2015/047153

申请日：2015-08-27

Applicant: QUALCOMM INCORPORATED

Inventor： AMARILIO, Lior ,  GOLUBITSKI, Alexander ,  HALLER, Haim, Hagay ,  KOLMAKOV, Felix ,  STHOEGER, Gilad

IPC: H03K5/13

CPC classification number: H03K5/133 ,  G06F1/10 ,  G06F13/4068 ,  G06F13/4221 ,  G11C19/00 ,  H03K5/13 ,  H03K2005/0015 ,  Y02D10/14 ,  Y02D10/151

Abstract: Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.

Abstract translation: 公开了延迟电路以及相关的系统和方法。 在一个方面，提供了一种延迟电路，其使用逻辑来准确地延迟输出使能信号以减少或避免从属装置内的数据危险。 延迟电路包括两个移位寄存器链，其被配置为基于慢时钟来接收输出使能信号。 第一移位寄存器链由快时钟的上升沿计时，并提供第一选通信号。 第二个移位寄存器链由快速时钟的下降沿提供时钟，并提供第二个选通信号。 该逻辑使用第一和第二选通信号以及输出使能信号来提供延迟的输出使能输出信号。 延迟电路为输出使能信号提供高度精确的时间延迟，从而减少或避免区域中的数据危险和节能方式。

公开(公告)号：WO2020256784A1

公开(公告)日：2020-12-24

申请号：PCT/US2019/068149

申请日：2019-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： GRAIF, Sharon ,  ZANGVIL, Meital ,  AMARILIO, Lior

IPC: G06F13/42

Abstract: Systems, methods, and apparatus are described. An apparatus provides a clock signal, transmits an address on a second line of the serial bus followed by a read/write bit configured to initiate a read transaction, and delays a pulse in the clock signal after transmitting the read/write bit. The pulse may be delayed for a first duration configured to accommodate a latency associated with a first slave device that is a participant in the read transaction. The apparatus may receive an acknowledgement from the first slave device while the pulse is being transmitted and may receive a first data byte from the first slave device after receiving the acknowledgment. The apparatus may stall the clock signal for a second duration after receiving the first data byte from the first slave device, and receive a second data byte from the first slave device after the acknowledgment.

公开(公告)号：WO2020046500A1

公开(公告)日：2020-03-05

申请号：PCT/US2019/043429

申请日：2019-07-25

Applicant: QUALCOMM INCORPORATED

Inventor： GRAIF, Sharon ,  AMARILIO, Lior ,  GAKMAN, Mark

IPC: G06F13/42 ,  G06F1/3234

Abstract: Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.

公开(公告)号：WO2019147719A1

公开(公告)日：2019-08-01

申请号：PCT/US2019/014818

申请日：2019-01-23

Applicant: QUALCOMM INCORPORATED

Inventor： AMARILIO, Lior ,  GRAIF, Sharon ,  MISHRA, Lalan Jee

IPC: G06F13/42

Abstract: Systems and methods for providing virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus are disclosed. While a SOUNDWIRE bus is particularly contemplated, other TDM buses may also be used to provide the benefits outlined herein. In particular, raw GPIO signals are placed into time slots on a TDM bus without requiring additional overhead or packaging. This arrangement allows all drops on a multi-drop bus to receive the GPIO signals substantially concurrently with latency measured in less than a frame period.

公开(公告)号：WO2019104073A1

公开(公告)日：2019-05-31

申请号：PCT/US2018/062075

申请日：2018-11-20

Applicant: QUALCOMM INCORPORATED

Inventor： AMARILIO, Lior ,  HERSHKO, Yuval Corey ,  STRAUSS, Nir

IPC: G06F13/362

Abstract: Systems and methods to transfer master duties to a slave on a communication bus are disclosed. A master of a communication bus determines that one or more slaves are capable of serving as a sub-master, including providing a clock signal and owning control information bits. Once that determination is made, the master may determine that processing within the master is not required for a particular activity on the bus. The master then alerts one such capable slave to prepare to assume sub-master duties. Once the slave confirms that the slave is ready to assume the sub-master duties, the master may transmit a handover frame on the bus, and the slave begins acting as a sub-master. The master may then enter a low-power state, which may promote power savings, reduce heat generation, and provide other advantages.

公开(公告)号：WO2016178761A1

公开(公告)日：2016-11-10

申请号：PCT/US2016/025477

申请日：2016-04-01

Applicant: QUALCOMM INCORPORATED

Inventor： GERBER, Nir ,  AMARILIO, Lior ,  GIL, Amit

IPC: G06F1/32

CPC classification number: G06F1/3253 ,  G06F13/385 ,  G06F2213/0042 ,  Y02D10/151

Abstract: Aspects disclosed in the detailed description include scheduled universal serial bus (USB) low-power operations. In this regard, in one aspect, a USB host controller determines a low-power operation schedule for a USB client device. The low-power operation schedule comprises one or more scheduled low-power operation periods, each corresponding to a respective entry time and a respective exit time. The USB host controller communicates the low-power operation schedule to the USB client device using one or more USB standard packets. By scheduling the one or more scheduled low-power operation periods with respective entry and exit times, the USB host controller or the USB client controller is able to start and end the one or more scheduled low-power operation periods without incurring additional signaling, thus improving efficiency of the USB low-power operation. Further, by communicating the low-power operation schedule using USB standard packets, it is possible to preserve compatibility with USB standards.

Abstract translation: 在详细描述中公开的方面包括调度的通用串行总线（USB）低功率操作。 在这方面，在一方面，USB主机控制器确定USB客户端设备的低功率操作调度。 低功率操作调度包括一个或多个调度的低功率操作周期，每个周期对应于相应的进入时间和相应的退出时间。 USB主机控制器使用一个或多个USB标准数据包将低功耗操作计划传送到USB客户端设备。 通过调度具有相应进入和退出时间的一个或多个调度的低功率操作时段，USB主机控制器或USB客户端控制器能够开始和结束一个或多个调度的低功率操作时段，而不会产生额外的信号，因此 提高USB低功耗操作的效率。 此外，通过使用USB标准分组传送低功率运行调度表，可以保持与USB标准的兼容性。

公开(公告)号：WO2016076990A1

公开(公告)日：2016-05-19

申请号：PCT/US2015/054863

申请日：2015-10-09

Applicant: QUALCOMM INCORPORATED

Inventor： HARIHARAN, Magesh ,  AMARILIO, Lior ,  ARCEO, Julio ,  BALATSOS, Aris ,  GRUBER, Hans Georg

IPC: H04R5/04 ,  G06F3/16 ,  G06F13/42 ,  H04M1/60

CPC classification number: H04L65/4069 ,  G06F3/162 ,  G06F13/4291 ,  H04R3/12 ,  H04R5/04 ,  H04R2420/09 ,  H04R2499/11

Abstract: Multi-channel audio alignment schemes are disclosed. One aspect of the present disclosure provides for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the Serial Low-power Inter-chip Media Bus (SLIMbus), such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.

Abstract translation: 公开了多声道音频对准方案。 本公开的一个方面提供了在音频源处跨越多个相关音频声道的音频样本的累积。 相关音频通道指示它们之间的相互关系，并且当所有相关音频通道都有数据要传输时，源将数据释放到串行低功耗片间媒体总线（SLIMbus）的时隙上，使得相关音频通道 在时隙的给定分段窗口内。 这个累积在每个分段窗口的边界处重复。 类似地，可以在音频接收器处执行累积。 如果来自所有相关接收器的状态信号指示已达到预定义阈值，则音频接收器内的组件只能读取接收到的数据。 通过提供这种累积选项，可以在多个音频数据通道中保持音频保真度。

公开(公告)号：WO2015117061A1

公开(公告)日：2015-08-06

申请号：PCT/US2015/014067

申请日：2015-02-02

Applicant: QUALCOMM INCORPORATED

Inventor： AMARILIO, Lior ,  AMON, Yossi ,  GERBER, Nir ,  SHACHAM, Assaf

IPC: H04L29/12 ,  G06F13/42

CPC classification number: G06F13/4221 ,  G06F13/364 ,  G06F13/409 ,  G06F13/4282 ,  G06F13/4291 ,  H04L61/2038 ,  H04L61/2046 ,  H04L61/2092 ,  H04L61/3005

Abstract: Device identification generation in electronic devices to allow external control, such as selection or reprogramming, of device identification for bus communications identification, is disclosed. In this manner, device identifications of electronic devices coupled to a common communications bus in a system can be selected or reprogrammed to ensure they are unique to avoid bus communications collisions. In certain aspects, to select or reprogram a device identification in an electronic device, an external source can be electrically coupled to the electronic device. The external source closes a circuit with a device identification generation circuit in the electronic device. The closed circuit provides a desired electrical characteristic detectable by the device identification generation circuit. The device identification generation circuit is configured to generate a device identification as a function of the detected electrical characteristics of the closed circuit from the external source.

Abstract translation: 公开了用于允许外部控制（例如选择或重新编程）用于总线通信识别的设备标识的电子设备中的设备识别生成。 以这种方式，可以选择或重新编程耦合到系统中的公共通信总线的电子设备的设备标识，以确保它们是唯一的，以避免总线通信冲突。 在某些方面，为了在电子设备中选择或重新编程设备识别，外部源可以电耦合到电子设备。 外部源在电子设备中用设备识别生成电路封闭电路。 封闭电路提供了可由设备识别生成电路检测的期望的电特性。 设备识别产生电路被配置为根据检测到的来自外部源的闭合电路的电特性来生成设备标识。

公开(公告)号：EP4323880A1

公开(公告)日：2024-02-21

申请号：EP22718363.9

申请日：2022-03-25

Applicant: QUALCOMM INCORPORATED

Inventor： MISHRA, Lalan Jee ,  PITIGOI-ARON, Radu ,  GRAIF, Sharon ,  AMARILIO, Lior ,  WIETFELDT, Richard, Dominic

IPC: G06F13/42

公开(公告)号：EP4237955A1

公开(公告)日：2023-09-06

申请号：EP21790705.4

申请日：2021-09-15

Applicant: QUALCOMM INCORPORATED

Inventor： BENJAMINI, Yiftach ,  AMARILIO, Lior ,  GRAIF, Sharon

IPC: G06F13/40 ,  G06F13/42