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    24.
    发明专利
    未知

    公开(公告)号：DE69030544T2

    公开(公告)日：1997-08-21

    申请号：DE69030544

    申请日：1990-08-28

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： GHEZZI PAOLO ,  RIVA CARLO ,  VALENTINI GRAZIA

    IPC: H01L21/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

    Abstract: The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor (20), sensing transistor (22) having a floating gate (5), control gate (10) with a capacitive coupling to the floating gate (5) and a tunnel area (23) with thin oxide (9), comprises a first step (29) involving the definition of active areas (41, 42) free of field oxide (11), a second step (30) involving an ionic implantation (10 min ) at a coupling area (24) between the control gate (10) and the floating gate (5), a third step (31) involving the creation of gate oxide (21) at the active areas (41, 42), a fourth step (32) involving an additional ionic implantation (10 sec , 8) at said coupling area (24) between the control gate (10) and the floating gate (5) and at said tunnel area (23), a fifth step (33) involving the removal of the gate oxide (21) superimposed over said areas (24, 23), a sixth step (34) involving the differentiated growth of coupling oxide (12) and tunnel oxide (9) at said coupling areas (24) and tunnel areas (23) and a seventh step (35) involving the deposition of a layer of polysilicon (5) constituting the floating gate.

    25.
    发明专利
    未知

    公开(公告)号：DE69012382T2

    公开(公告)日：1995-02-16

    申请号：DE69012382

    申请日：1990-03-12

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  RIVA CARLO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

    Abstract: A reference cell for reading EEPROM memory devices, capable of discharging any charges present in its own floating gate (3) without varying the geometry of the cell with respect to that of the associated memory cells and without requiring specific manufacturing steps. For this purpose, a switch element, for example a diode (D1), is provided between the floating gate (3) and the substrate (11) of the device and discharges any charges present in the floating gate toward the substrate during the cell idle state (in the absence of read signals)

    26.
    发明专利
    未知

    公开(公告)号：IT1237666B

    公开(公告)日：1993-06-15

    申请号：IT2222889

    申请日：1989-10-31

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

    IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L

    Abstract: The manufacturing process comprises a first step of formation of an N type sink (2) on a single-crystal silicon substrate (1), a second step of formation of an active area (14) on the surface of said sink (2), a third step of implantation of N- dopant in a surface region (4) of the sink (2) inside said active area (14), a fourth step of growth of a layer (5) of gate oxide over said region with N- dopant, a fifth step of N+ implantation (6; 9) inside said N- region, a sixth step of P+ implantation (7; 12) in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts (8, 18; 13, 23, 33) for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

    30.
    发明专利
    未知

    公开(公告)号：DE69025854T2

    公开(公告)日：1996-08-01

    申请号：DE69025854

    申请日：1990-10-24

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

    IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L21/82 ,  H01L27/02 ,  G11C16/04

    Abstract: The manufacturing process comprises a first step of formation of an N type sink (2) on a single-crystal silicon substrate (1), a second step of formation of an active area (14) on the surface of said sink (2), a third step of implantation of N- dopant in a surface region (4) of the sink (2) inside said active area (14), a fourth step of growth of a layer (5) of gate oxide over said region with N- dopant, a fifth step of N+ implantation (6; 9) inside said N- region, a sixth step of P+ implantation (7; 12) in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts (8, 18; 13, 23, 33) for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

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