DISPOSITIF DE DEPHASAGE POUR RESEAU D'ANTENNES

    公开(公告)号:FR2969835A1

    公开(公告)日:2012-06-29

    申请号:FR1061173

    申请日:2010-12-23

    Abstract: Dispositif comprenant des moyens de traitement (MT), des voies d'émission (VE1, ... VEn), un réseau d'antennes pour émettre des signaux comportant plusieurs antennes (A11 ... Ain) respectivement associées aux voies d'émission, plusieurs convertisseurs numérique analogique (DAC) et plusieurs moyens de déphasage (MD1, ...MDn) respectivement associés aux antennes, lesdits moyens de déphasages (MD1, ...MDn) étant placés entre les moyens de traitement (MT) et les convertisseurs numérique analogique (DAC) et comportant des filtres passe-tout numériques de type FIR (PT), les moyens de traitement comprenant des moyens de commande (MC) configurés pour ajuster les coefficients et/ou l'ordre des filtres passe-tout de type FIR.

    23.
    发明专利
    未知

    公开(公告)号:FR2911448B1

    公开(公告)日:2009-07-10

    申请号:FR0752700

    申请日:2007-01-16

    Abstract: A bulk acoustic wave resonator has an adjustable resonance frequency. A piezoelectric element is provided having first and second electrodes. A switching element is provided in the form of a MEMS structure which is deformable between a first and second position. The switching element forms an additional electrode that is selectively disposed on top of, and in contact with, one of the first and second electrodes. This causes a total thickness of the electrode of the resonator to be changed resulting in a modification of the resonance frequency of the resonator.

    25.
    发明专利
    未知

    公开(公告)号:DE69930365T2

    公开(公告)日:2006-12-07

    申请号:DE69930365

    申请日:1999-12-16

    Inventor: BELOT DIDIER

    Abstract: A built-in circuit includes a semiconductor substrate (SB) with a bottom part (PSB) and upper layer (CSB) strongly doped that the bottom part. A first block (BC3) and a second block (BC1) are formed in the upper part of the substrate. An isolating device is arranged closed to the second block (BC1) and includes an isolating circuit (CRS) linked to the bottom part of the substrate (PSB). A mass connection (PTMD1) provide a minimal impedance at a given frequency.

    27.
    发明专利
    未知

    公开(公告)号:DE69825527D1

    公开(公告)日:2004-09-16

    申请号:DE69825527

    申请日:1998-05-22

    Inventor: BELOT DIDIER

    Abstract: The receiving circuit for bits transmitted on an asynchronous signal (Din) consists of a circuit which provides a reconstructed clock from an asynchronous signal. The clock is designed to sample the asynchronous signal to form a synchronised output signal (Ds). The receiver also has a reception error detection circuit. The error detection circuit consists of a front detector (21, 22, 24, 25), which provides a detection pulse (UP, DN) for each leading edge in a predetermined direction for the asynchronous signal. An alarm circuit (27, 28) generates an warning signal when a leading edge of a synchronous signal (Ds) survives outside a detection pulse (UP, DP).

    30.
    发明专利
    未知

    公开(公告)号:FR2818054A1

    公开(公告)日:2002-06-14

    申请号:FR0016034

    申请日:2000-12-08

    Abstract: The invention concerns a transmission-reception head of a high frequency signal in the form of an integrated circuit comprising a transmission amplifier (23) and a reception amplifier (22). The transmission amplifier transmission terminals and the reception amplifier reception terminals are interconnected in a common transmission-reception terminal (20). The head comprises means for selecting one of the amplifiers and means for placing the other amplifier in a state of high impedance, relative to the transmission-reception terminal.

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