公开(公告)号：FR2794598A1

公开(公告)日：2000-12-08

申请号：FR9906963

申请日：1999-06-02

Applicant: ST MICROELECTRONICS SA

Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL ,  MAZZONI SIMONE

IPC: G06F17/14 ,  G06T1/60 ,  H04J11/00 ,  H04L27/26 ,  H04L27/32

Abstract: The inverse Fourier transform parallel pipeline processing technique inputs initial samples (Ck) of a digital stream to an interlaced processing unit. An auxiliary complex sample (Ak) is formed from initial input. Different stages of inverse transformation are carried out using pipeline architecture processing (DF), using two different memories (MMA,MMB), the elementary processing being separated into two parts.

公开(公告)号：DE60021479T2

公开(公告)日：2006-05-24

申请号：DE60021479

申请日：2000-05-25

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL ,  MAZZONI SIMONE

IPC: G06F17/14 ,  H04L27/26 ,  G06T1/60 ,  H04J11/00

Abstract: The inverse Fourier transform parallel pipeline processing technique inputs initial samples (Ck) of a digital stream to an interlaced processing unit. An auxiliary complex sample (Ak) is formed from initial input. Different stages of inverse transformation are carried out using pipeline architecture processing (DF), using two different memories (MMA,MMB), the elementary processing being separated into two parts.

公开(公告)号：FR2850768B1

公开(公告)日：2005-11-18

申请号：FR0301197

申请日：2003-02-03

Applicant: ST MICROELECTRONICS SA

Inventor： CAMBONIE JOEL

IPC: G06F15/78 ,  H03K19/177

Abstract: The device has a programmable circuit (FPGA) including programming units mutually connected by one configurable network interconnection. The circuit (FPGA) generates clock and control signals for arithmetic cells. The arithmetic cells are mutually connected by another configurable network interconnection. The cells have arithmetic logical unit, an address generator and a memory.

公开(公告)号：DE69830971D1

公开(公告)日：2005-09-01

申请号：DE69830971

申请日：1998-12-09

Applicant: ST MICROELECTRONICS SA

Inventor： CAMBONIE JOEL

IPC: G06F17/14

公开(公告)号：DE60002371D1

公开(公告)日：2003-06-05

申请号：DE60002371

申请日：2000-01-25

Applicant: ST MICROELECTRONICS SA

Inventor： MAZZONI SIMONE ,  CAMBONIE JOEL

IPC: H04J11/00 ,  H04L27/26

Abstract: The circuit takes a sample from the header and re-copies this at the end of the signal. The circuit generates a cyclical symbol prefix composed of a series of samples in the time domain. The prefix is the reproduction of the last symbol samples in the symbol header. The symbol is obtained by inverse Fourier transformation of the complex coefficients corresponding to the respective frequencies. The circuit includes a device (22) for dephasing each complex coefficient of a value proportional to its frequency. A memory (24) is provided for storing the samples of the start of the symbol, and a further circuit (16) is provided for re-copying the memorised samples at the end of the symbol.

公开(公告)号：FR2788869A1

公开(公告)日：2000-07-28

申请号：FR9900770

申请日：1999-01-25

Applicant: ST MICROELECTRONICS SA

Inventor： CAMBONIE JOEL ,  MAZZONI SIMONE

IPC: G06F17/14