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    3.
    发明专利
    未知

    公开(公告)号：DE60019367D1

    公开(公告)日：2005-05-19

    申请号：DE60019367

    申请日：2000-05-26

    Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

    Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL

    IPC: H04L27/00 ,  G06T1/60 ,  H04J11/00 ,  H04L1/00 ,  H04L27/26

    Abstract: A sequential development of exit N samples (Ck) and their sequential delivery in a natural order (k) is obtained from a second addressing sequence containing natural and reversed orders. The phase of subsequent processing of the symbol auxiliary sequence (UK) temporally overlaps with respective phases of corresponding processing of the previous (UK-i) and the next symbol (UK+i). The addressing of the two memorials is successively and performed alternately according to the first and the second addresses sequence. An Independent claim is included for: (a) a device for transforming two groups of samples

    METHOD FOR CONVERTING COMPLEX SYMBOL TO REAL NUMBER DATA
    4.
    发明专利
    METHOD FOR CONVERTING COMPLEX SYMBOL TO REAL NUMBER DATA 失效

    公开(公告)号：JP2001005801A

    公开(公告)日：2001-01-12

    申请号：JP2000160149

    申请日：2000-05-30

    Applicant: ST MICROELECTRONICS ,  FRANCE TELECOM

    Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL ,  MAZZONI SIMONE

    IPC: G06F17/14 ,  G06T1/60 ,  H04J11/00 ,  H04L27/26

    Abstract: PROBLEM TO BE SOLVED: To optimize the latency of a memory by executing inverse Fourier transformation in a pipeline structure using a random access memory(RAM). SOLUTION: This method is composed of interleave type processing provided with a preprocessing phase for preparing an auxiliary symbol composed of an auxiliary complex sample Ak concerning each initial symbol and a processing phase including the inverse Fourier transformation of a size N concerning each auxiliary symbol, and the transmission of 2N pieces of real number output data xp. The various stages of a graph are executed inside the pipeline structure DF. When the initial symbol is received, two different RAMs (MMA and MMB) are simultaneously used, the auxiliary symbol corresponding to this initial symbol is stored in the first memory MMA and on the basis of contents in the second memory MMB, basic processing corresponding to the first stage of the graph is executed. Each time the initial symbol is newly received, two memories are switched.

    METHOD AND DEVICE FOR CONVERTING STREAM OF REAL NUMBER INPUT DATA INTO COMPLEX OUTPUT SYMBOL STREAM
    5.
    发明专利
    METHOD AND DEVICE FOR CONVERTING STREAM OF REAL NUMBER INPUT DATA INTO COMPLEX OUTPUT SYMBOL STREAM 失效

    公开(公告)号：JP2001024621A

    公开(公告)日：2001-01-26

    申请号：JP2000171894

    申请日：2000-06-08

    Applicant: ST MICROELECTRONICS ,  FRANCE TELECOM

    Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL

    IPC: H04L27/00 ,  G06T1/60 ,  H04J11/00 ,  H04L1/00 ,  H04L27/26

    Abstract: PROBLEM TO BE SOLVED: To efficiently convert real number data into a complex symbol, when receiving a carrier to be transmitted via a telephone line and subjected to phase modulation and amplitude modification. SOLUTION: A group stream to be formed from 2N pieces of the real number input data is converted into a complex number output symbol stream to be formed from N complex output samples by an interleave type processing. The interleave type processing is constituted of a pre-processing and a post- processing. The post-processing is timewisely nested regarding two continuos symbols, two memories of the same size which can be individually addressed are used and address specification of the two memories is executed continuously and alternately in the natural order and the reverse order, while being synchronized with a symbol clock signal.

    7.
    发明专利
    未知

    公开(公告)号：FR2794921B1

    公开(公告)日：2001-09-14

    申请号：FR9907495

    申请日：1999-06-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL

    IPC: H04L27/00 ,  G06T1/60 ,  H04J11/00 ,  H04L1/00 ,  H04L27/26 ,  H04L27/32

    Abstract: A sequential development of exit N samples (Ck) and their sequential delivery in a natural order (k) is obtained from a second addressing sequence containing natural and reversed orders. The phase of subsequent processing of the symbol auxiliary sequence (UK) temporally overlaps with respective phases of corresponding processing of the previous (UK-i) and the next symbol (UK+i). The addressing of the two memorials is successively and performed alternately according to the first and the second addresses sequence. An Independent claim is included for: (a) a device for transforming two groups of samples

    A compact turbo-decoder having high efficiency, comprises two sets of processors for computing in parallel the syndromes and for updating in parallel the block, respectively
    8.
    发明专利
    A compact turbo-decoder having high efficiency, comprises two sets of processors for computing in parallel the syndromes and for updating in parallel the block, respectively 未知

    公开(公告)号：FR2834146A1

    公开(公告)日：2003-06-27

    申请号：FR0116619

    申请日：2001-12-20

    Applicant: ST MICROELECTRONICS SA

    Inventor： MEJEAN PHILIPPE ,  CAMBONIE JOEL

    IPC: H03M13/29 ,  H04L1/00

    Abstract: The method for decoding the data encoded by blocks by use of a turbo-code comprises the steps of implementing different algorithms so that at least two steps are suited for applying in parallel to different blocks of data. The steps comprise a first step for computing a syndrome and a second step for updating the block by use of the syndrome computed in the course of the first step. The first step is carried out on a first part of the first block, and the second step is carried out on a second part of the first block or a part of the second block. In the first step a set of n first processors (PROC1) is operated in parallel on n rows, respectively columns, of a block, and in the second step a set of m second processors (PROC2) is operated in parallel on m rows, respectively columns, of a block. A block of data is of dimension 32 x 32 and n = m = 16. The data are coded by a coding of type BCH or extended BCH, and the updating is by use of an algorithm of Berlekamp or Euclide followed by an algorithm of Chase-Pyndiah. The decoding circuit (20) is claimed and comprises the first set of processors (PROC1) for computing the syndromes in parallel, where each syndrome corresponds to a syndrome of a row, respectively column, of the first part of the first block of data, and the second set of processors (PROC2) for updating in parallel the rows, respectively columns, of the second part of the first block or a part of the second block of data. The decoding circuit also comprises a first group of memory stores (A) which includes the random-access memories (RAM1,RAM1',RAM1'',RAM1''') including two optional (RAM10,RAM10') with access along rows, which can store at least two successive blocks of data, a second group of memory stores (B) including the random-access memories (RAM12,RAM13) as the working memory, a fourth group of memory stores (D) including the random-access memories (RAM14,RAM15) as the working memory or the buffer memory, a random-access memory (RAM18) for storing a block after processing and an optional FORMAT module connected to output (OUT'), a processing block 922) at input (IN') with a depuncturing module (DEPUNC), a bus (25), and a controller (27). Each memory store has a direct access to the bus. The decoding circuit allows to carry out 4 consecutive iterations in real time for the data flow rate of up to 54 Mbit/s and the blocks of dimension 32x32.

    9.
    发明专利
    未知

    公开(公告)号：FR2794921A1

    公开(公告)日：2000-12-15

    申请号：FR9907495

    申请日：1999-06-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： CAMBONIE JOEL ,  MEJEAN PHILIPPE ,  BARTHEL DOMINIQUE ,  LIENARD JOEL

    IPC: H04L27/00 ,  G06T1/60 ,  H04J11/00 ,  H04L1/00 ,  H04L27/26 ,  H04L27/32

    Abstract: A sequential development of exit N samples (Ck) and their sequential delivery in a natural order (k) is obtained from a second addressing sequence containing natural and reversed orders. The phase of subsequent processing of the symbol auxiliary sequence (UK) temporally overlaps with respective phases of corresponding processing of the previous (UK-i) and the next symbol (UK+i). The addressing of the two memorials is successively and performed alternately according to the first and the second addresses sequence. An Independent claim is included for: (a) a device for transforming two groups of samples

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