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    Voltage-limiting circuit for use at the output of an over-voltage circuit such as charge pump used for obtaining voltage higher than the supply voltage, in particular for memory circuits
    22.
    发明专利
    Voltage-limiting circuit for use at the output of an over-voltage circuit such as charge pump used for obtaining voltage higher than the supply voltage, in particular for memory circuits 未知

    公开(公告)号：FR2847717A1

    公开(公告)日：2004-05-28

    申请号：FR0214820

    申请日：2002-11-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： DEVIN JEAN

    IPC: H02H9/04 ,  H01L29/86 ,  G05F1/46 ,  H03K17/08

    Abstract: The voltage-limiting circuit (16) comprises at least one p-n junction (DPN) having a breakdown voltage (Vppmax) defining a trigger threshold of the circuit on the basis of which the p-n junction is conducting by the avalanche effect. The circuit also comprises a load (LD) in series with the p-n junction for limiting the avalanche current (I1), and at least one switch (SW) in parallel with the p-n junction and the load. The switch (SW) is open when the junction is nonconducting and closed when the junction is conducting. The load (LD) is chosen so that the avalanche current (I1) passing through the p-n junction is at least two times below the current (I2) passing through the switch (SW) when the circuit is triggered. The p-n junction is a junction of an n-MOS transistor connected as a diode, and the load (LD) comprises a p-MOS transistor. The switch (SW) comprises a p-MOS transistor which is connected as a current0mirror with the p-MOS transistor of the load (LD). An integrated circuit (claimed) comprises the voltage-limiting circuit (claimed) connected at the output of a voltage generator delivering a voltage (Vpp), and the voltage generator is an overvoltage circuit. A voltage regulator (claimed) comprises the voltage-limiting circuit and means for delivering a logic signal (on/off) when the circuit is triggered. A method (claimed) for limiting a voltage (Vpp) by use of a p-n junction is implemented by the circuit and consists in limiting the avalance current by a load, and closing a switch in parallel when the junction is conducting.

    23.
    发明专利
    未知

    公开(公告)号：FR2803142A1

    公开(公告)日：2001-06-29

    申请号：FR9916563

    申请日：1999-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： BERTRAND BERTRAND ,  DEVIN JEAN

    IPC: H03K17/16 ,  H03K17/08 ,  G11C7/12 ,  G11C16/02 ,  H03K17/14

    Abstract: The integrated circuit (20) comprises an output MOS transistor (Tout) connected to a data transmission line (31) presenting a determined capacitance (Cbus), where the gate of transistor is driven by a logic circuit (11) present in the integrated circuit which receives a determined supply voltage (Vccd), and a gate-biasing circuit (41) for lowering the gate-source voltage (Vgs) in the on-state of transistor with respect to the supply voltage, which would be set by the output of logic circuit in the absence of gate-biasing circuit. The lengthening of fall time while retaining the operating point (Vol, Iol) also includes an increase in the width/length ratio (W/L) of transistor gate in an implementation stage. The gate-biasing circuit (41) comprises two transistors connected in series, each connected as a diode. The first transistor of MOS type is substantially identical to the output transistor. The gate-source voltage (Vgs) is less than 2 V to set the transistor in the on-state. The output transistor (Tout) has the ratio W/L corresponding to the operating point in low state in conformity with the specifications of 12C bus and the fall time (Tfall) of output signal equal at least to 20 nanoseconds. The method for lengthening the fall time includes the lowering of gate-source voltage (Vgs), and the increased ratio W/L of transistor gate. The integrated circuit is in the form of an EEPROM, and the output stage (40) is laid out to deliver the data read in the memory.

    24.
    发明专利
    未知

    公开(公告)号：DE69800797D1

    公开(公告)日：2001-06-21

    申请号：DE69800797

    申请日：1998-01-22

    Applicant: ST MICROELECTRONICS SA

    Inventor： DEVIN JEAN ,  BRIGATI ALESSANDRO ,  LECONTE BRUNO

    IPC: G11C16/02 ,  G11C16/10 ,  G11C16/12 ,  G11C16/06

    Abstract: In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.

    26.
    发明专利
    未知

    公开(公告)号：DE602004008170T2

    公开(公告)日：2008-04-30

    申请号：DE602004008170

    申请日：2004-06-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： DEVIN JEAN

    IPC: G11C16/22 ,  G11C8/20 ,  G11C11/22

    Abstract: The circuit has a non-volatile memory zone (3) for storing identification codes, and a programming pin (4) for programming the memory zone. A register (5) that can be programmed only once, stores a state indicating whether the memory zone has been programmed. A module (6) blocks the programming of the memory zone when the register indicates that the memory zone has been programmed. An independent claim is also included for a method of using a memory circuit.

    27.
    发明专利
    未知

    公开(公告)号：DE602004008170D1

    公开(公告)日：2007-09-27

    申请号：DE602004008170

    申请日：2004-06-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： DEVIN JEAN

    IPC: G11C16/22 ,  G11C8/20 ,  G11C11/22

    Abstract: The circuit has a non-volatile memory zone (3) for storing identification codes, and a programming pin (4) for programming the memory zone. A register (5) that can be programmed only once, stores a state indicating whether the memory zone has been programmed. A module (6) blocks the programming of the memory zone when the register indicates that the memory zone has been programmed. An independent claim is also included for a method of using a memory circuit.

    28.
    发明专利
    未知

    公开(公告)号：DE60109958D1

    公开(公告)日：2005-05-12

    申请号：DE60109958

    申请日：2001-11-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： CAVALERI PAOLA ,  LECONTE BRUNO ,  ZINK SEBASTIEN ,  DEVIN JEAN

    IPC: G11C16/02 ,  G11C16/06 ,  G11C16/16 ,  G11C16/34

    Abstract: The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.

    29.
    发明专利
    未知

    公开(公告)号：DE69717768D1

    公开(公告)日：2003-01-23

    申请号：DE69717768

    申请日：1997-10-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： DEVIN JEAN

    IPC: G11C7/14 ,  G11C7/00 ,  G11C16/06

    Abstract: The EPROM memory includes a number of cells (7) each including a floating gate transistor. The cells are connected to bit lines (8-10) and word lines (11-14) to define an array controlled by a control gate (5) connected to a word line (11). An address signal (ADR) is transmitted to a decoder (16,17) which selects the cell to be read. Reading circuits (18-20) are connected to the end of the bit lines (8-10). The connection is made only to the bit line selected by the decoder. A supplementary bit line (22) is connected to additional memory cells (23-26) which include only simple transistors. The supplementary bit line is connected to a reading circuit (27) via a transistor (29).

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