公开(公告)号：DE69611325D1

公开(公告)日：2001-02-01

申请号：DE69611325

申请日：1996-06-17

Applicant: ST MICROELECTRONICS SA

Inventor： GUEDJ MARC ,  BRIGATI ALESSANDRO ,  AULAS MAXENCE ,  DEMANGE NICOLAS

IPC: G11C17/00 ,  G11C16/06 ,  H03K17/693 ,  H03K19/00

Abstract: A first input terminal receives a positive voltage (HPV) and a second input terminal (3) receives a negative input voltage (HVN). A first control logic signal (CS1) is applied to the pair of transistors (9, 10) to select the voltage at the output (4). A third input terminal (32) may be added to receive a second positive voltage (VP) which is connected to the output via a third transistor (31). A second control logic signal (CS2) is applied to an input terminal (33) and together with the first control signal by means of the control circuits (11, 13, 14, 15, 16, 30, 34) determines the voltage applied to the gates of the transistors (9, 10, 31) so as to select one of the inputs to present at the output.

公开(公告)号：DE69815590D1

公开(公告)日：2003-07-24

申请号：DE69815590

申请日：1998-03-20

Applicant: ST MICROELECTRONICS SA

Inventor： BRIGATI ALESSANDRO ,  DEVIN JEAN ,  LECONTE BRUNO

IPC: G11C16/02 ,  G06F12/06 ,  G11C7/00 ,  G11C8/12 ,  G11C8/00

Abstract: The IC (1) has two memories (2,3) each controlled by a microprocessor (4,6). Each microcontroller has a circuit (13,14) executing the memory read or write operation. The read or write operations are carried out independent of the selected signal (SS1,SS2). A selection circuit (5) allows one of the memory circuits to be selected.

公开(公告)号：DE69800797T2

公开(公告)日：2001-11-22

申请号：DE69800797

申请日：1998-01-22

Applicant: ST MICROELECTRONICS SA

Inventor： DEVIN JEAN ,  BRIGATI ALESSANDRO ,  LECONTE BRUNO

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/12 ,  G11C16/06

Abstract: In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.

公开(公告)号：DE69800797D1

公开(公告)日：2001-06-21

申请号：DE69800797

申请日：1998-01-22

Applicant: ST MICROELECTRONICS SA

Inventor： DEVIN JEAN ,  BRIGATI ALESSANDRO ,  LECONTE BRUNO

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/12 ,  G11C16/06

Abstract: In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.

公开(公告)号：DE69611325T2

公开(公告)日：2001-05-23

申请号：DE69611325

申请日：1996-06-17

Applicant: ST MICROELECTRONICS SA

Inventor： GUEDJ MARC ,  BRIGATI ALESSANDRO ,  AULAS MAXENCE ,  DEMANGE NICOLAS

IPC: G11C17/00 ,  G11C16/06 ,  H03K17/693 ,  H03K19/00

Abstract: A first input terminal receives a positive voltage (HPV) and a second input terminal (3) receives a negative input voltage (HVN). A first control logic signal (CS1) is applied to the pair of transistors (9, 10) to select the voltage at the output (4). A third input terminal (32) may be added to receive a second positive voltage (VP) which is connected to the output via a third transistor (31). A second control logic signal (CS2) is applied to an input terminal (33) and together with the first control signal by means of the control circuits (11, 13, 14, 15, 16, 30, 34) determines the voltage applied to the gates of the transistors (9, 10, 31) so as to select one of the inputs to present at the output.