公开(公告)号：FR2826772B1

公开(公告)日：2005-03-04

申请号：FR0108455

申请日：2001-06-27

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  VAUTRIN FLORENT

IPC: G11C11/406

Abstract: A device and a method for refreshing the voltage of a circuit line that provides the capability of bringing the circuit line to a ground voltage or to a first voltage. The method provides storing the circuit line voltage in a capacitor; and controlling, by means of the stored voltage, a switch connecting the circuit line to a second voltage of absolute value greater than the first voltage, whereby the circuit line is set to the second voltage if, during the step of storing, the circuit line was at the first voltage.

公开(公告)号：DE60101248D1

公开(公告)日：2003-12-24

申请号：DE60101248

申请日：2001-09-03

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C15/04

Abstract: The content-addressed memory cell comprises the first storage subcell with transistors (T1,T2) in series and inverters (INV1,INV2) in antiparallel connection, a comparison subcell with transistors (PA,PB) in series controlling a transistor (PC) which is connected in series with a blocking transistor (PD), and the second storage subcell with transistors (T3,T4) in series and inverters (INV3,INV4) in antiparallel connection controlling the blocking transistor (PD). The transistors (T1,T2,T3,T4) are with n-type conductivity channel, and the transistors (PA,PB,PC,PD) are with p-type conductivity channel. The memory cell is implemented in the form of an integrated circuit wherein the transistors with p-type conductivity channel are implemented in the same n-type well which occupies substantially half of the cell surface. The first storage subcell is connected between the first set of bit lines (BL1,/BL1), and the gates of transistors (T1,T2) are connected to the first word line (WL1). The second storage subcell is connected between the second set of bit lines (BL2,/BL2), and the gates of transistors (T3,T4) are connected to the second word line (WL2). The blocking transistor (PD) is connected to the match line (MATCH). In the integrated circuit implementation, the transistors (T1,T2,T3,T4) are implemented in a substantially aligned fashion, the same as the n-type transistors of inverters (INV1,INV2,INV3,INV4), and the transistors (PA,PB,PC,PD) are also implemented in a substantially aligned fashion as well as the p-type transistors of inverters (INV1,INV2,INV3,INV4).

公开(公告)号：FR2809526B1

公开(公告)日：2003-07-25

申请号：FR0006645

申请日：2000-05-24

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C7/06 ,  G11C17/12 ,  G11C7/12

Abstract: The invention concerns a ROM circuit ( 40 ) including columns of storage cells, each column being connected to a bit site (BLi, BLi+1), wherein the columns are arranged in groups of two adjacent columns, each column of a group capable of being selectively activated relative to the other column of the group, thereby enabling the elimination of a connection to the ground of columns and the design of efficient reading amplifiers.

公开(公告)号：FR2827443A1

公开(公告)日：2003-01-17

申请号：FR0109190

申请日：2001-07-11

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE PHILIPPE ,  HUGUES JEAN FRANCOIS ,  FERRANT RICHARD

IPC: H03K19/003 ,  H03K19/007

Abstract: The protection circuit receives an initial clock signal and transmits at least one, in particular three or four, resultant clock signals to a downstream circuit. The protection circuit comprises an input circuit receiving the input clock signal and generating two intermediate clock signals which are images of the initial clock signal, and a recombination circuit which delivers the resultant clock signals which are the images of the intermediate clock signals if the intermediate clock signals are identical, or inactive, that is corresponding to a high impedance, if the intermediate signals are different, as in an event causing a peak in current or voltage. The input circuit comprises two buffers, preferentially distanced in the circuit design, whose inputs are connected together to the circuit input, and whose outputs deliver the intermediate clock signals . The recombination circuit is specified in three embodiments, and comprises complex and simple inverter circuits. In the first embodiment, it comprises three complex inverter circuits, where the first complex inverter comprises two p-type and two n-type transistors connected in series between a supply voltage terminal and a ground; the gates of p-type and n-type transistors in pairs are connected to two inputs of the complex inverter. In the second embodiment, the recombination circuit comprises one complex inverter and three simple inverters; the simple inverter comprises a pair of transistors, p-type and n-type, connected in series between a supply voltage terminal and a ground; the gates of transistors are connected together to the inverter input; the recombination circuit delivers four resultant clock signals. In the third embodiment, the recombination circuit comprises two complex inverters and two simple inverters, and delivers four resultant clock signals. A clock circuit for an integrated circuit as claimed comprises the protection circuit, where the protection circuit is connected between the circuit input utilizing the clock signal and a part of a branch of the clock circuit.

公开(公告)号：FR2813698B1

公开(公告)日：2002-11-29

申请号：FR0011242

申请日：2000-09-04

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C15/04 ,  G11C11/40 ,  G06F12/08

Abstract: The content-addressed memory cell comprises the first storage subcell with transistors (T1,T2) in series and inverters (INV1,INV2) in antiparallel connection, a comparison subcell with transistors (PA,PB) in series controlling a transistor (PC) which is connected in series with a blocking transistor (PD), and the second storage subcell with transistors (T3,T4) in series and inverters (INV3,INV4) in antiparallel connection controlling the blocking transistor (PD). The transistors (T1,T2,T3,T4) are with n-type conductivity channel, and the transistors (PA,PB,PC,PD) are with p-type conductivity channel. The memory cell is implemented in the form of an integrated circuit wherein the transistors with p-type conductivity channel are implemented in the same n-type well which occupies substantially half of the cell surface. The first storage subcell is connected between the first set of bit lines (BL1,/BL1), and the gates of transistors (T1,T2) are connected to the first word line (WL1). The second storage subcell is connected between the second set of bit lines (BL2,/BL2), and the gates of transistors (T3,T4) are connected to the second word line (WL2). The blocking transistor (PD) is connected to the match line (MATCH). In the integrated circuit implementation, the transistors (T1,T2,T3,T4) are implemented in a substantially aligned fashion, the same as the n-type transistors of inverters (INV1,INV2,INV3,INV4), and the transistors (PA,PB,PC,PD) are also implemented in a substantially aligned fashion as well as the p-type transistors of inverters (INV1,INV2,INV3,INV4).

公开(公告)号：FR2784493B1

公开(公告)日：2001-11-16

申请号：FR9812843

申请日：1998-10-09

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C11/4074 ,  G11C11/40

公开(公告)号：FR2784783A1

公开(公告)日：2000-04-21

申请号：FR9813168

申请日：1998-10-16

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C16/04 ,  G11C29/00 ,  G11C17/12

公开(公告)号：FR2784782A1

公开(公告)日：2000-04-21

申请号：FR9813170

申请日：1998-10-16

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C11/404 ,  G11C11/40

Abstract: The ROM/RAM architecture has an integrated circuit with a matrix of memory cells (1) and a selection transistor (T) with storage capacitor (C). The node (s) can be set to read or write and depending on the charge state of the capacitor and setting, to one of two voltage rails.

公开(公告)号：DE69907800T2

公开(公告)日：2004-04-08

申请号：DE69907800

申请日：1999-03-26

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  FERRANT RICHARD

IPC: G11C7/10 ,  G11C7/00

Abstract: The present invention relates to a DRAM circuit including a plurality of memory cells organized in an array, including switches for associating with each end of each column of the array at least two latches controlled independently from each other to store data written into or read from the considered column.

公开(公告)号：FR2827443B1

公开(公告)日：2004-03-26

申请号：FR0109190

申请日：2001-07-11

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE PHILIPPE ,  HUGUES JEAN FRANCOIS ,  FERRANT RICHARD

IPC: H03K19/003 ,  H03K19/007

Abstract: A circuit (200) for protection against voltage or current spikes receives an initial clock signal (CI) and transmits at least one resultant clock signal (CN1, CN2, CP1, CP2) to a downstream circuit. This resultant clock signal is inactive if a random voltage or current spike appears upstream. This averts the possibility of disturbing the operation of the downstream circuit. Application to the protection of clock circuits for integrated circuits.