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    21.
    发明专利
    未知

    公开(公告)号：FR2819631B1

    公开(公告)日：2003-04-04

    申请号：FR0100414

    申请日：2001-01-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： MENUT OLIVIER ,  GRIS YVON

    IPC: H01L21/76 ,  H01L21/20 ,  H01L21/205 ,  H01L21/329 ,  H01L21/762 ,  H01L21/822 ,  H01L27/04 ,  H01L29/861

    Abstract: Semiconductor single crystal substrate is made by forming an initial single crystal substrate (1) having lattice discontinuity locally on its surface, amorphizing the lattice around periphery of a recess formed at the discontinuity, depositing amorphous material the same as that of initial substrate on the obtained structure, and thermally annealing, to recrystallize the amorphous material. Production of a semiconductor single crystal substrate involves: (a) Forming an initial single crystal substrate (1), then successively depositing on the initial substrate (1) a first layer (2) of a first material and a second layer (3) of a second material, and etching a trench (4) which is subsequently filled with a filling material and which forms a lattice discontinuity in the single crystal lattice; (b) Performing selective etching with respect to the second layer (3), the first layer (2) and an upper part of the filling material of the trench (4), so as to form lateral cavities and a recess at the level of the single crystal discontinuity, and removing the second layer (3); (c) Amorphizing the single crystal lattice around the periphery of the recess; (d) Depositing a layer of amorphous material having the same chemical composition as that of the initial substrate (1) on the obtained structure; and (e) Thermally annealing the structure, in order to recrystallize the amorphous material so that it becomes continuous with the single crystal lattice of the initial substrate. The initial substrate is selected from silicon, germanium, silicon carbide, gallium arsenide, and an alloy containing at least some of these materials. The amorphization stage (c) involves localized ion implantation around the recess by using a mask. Amorphization is self-aligned on the trench (4). Either before or after stage (e), the surface of the structure is planarized, preferably by chemical-mechanical polishing. An Independent claim is given for an integrated circuit comprising a single crystal silicon substrate produced by the above process, and comprising at least two adjacent transistors produced in the body of the substrate that includes at least one buried trench forming an isolating trench separating the buried layers adjacent to the transistors.

    Laterally functioning bipolar transistor with a radically different structure to augment output current without augmentation of surface congestion
    22.
    发明专利
    Laterally functioning bipolar transistor with a radically different structure to augment output current without augmentation of surface congestion 未知

    公开(公告)号：FR2824666A1

    公开(公告)日：2002-11-15

    申请号：FR0106141

    申请日：2001-05-09

    Applicant: ST MICROELECTRONICS SA

    Inventor： MENUT OLIVIER ,  JAOUEN HERVE

    IPC: H01L29/06 ,  H01L29/10 ,  H01L29/735

    Abstract: A laterally functioning bipolar transistor incorporates: (a) an emitter region (17) arranged in an insulated seat (11, 150) cut in a semiconductor substrate; (b) an extrinsic collector region (16) arranged in a second insulated seat (3, 150) cut in the semiconductor substrate (SB) and separated laterally from the first seat by a zone (20) of the substrate; (c) an intrinsic collector region situated in the separating zone in contact with the extrinsic collector region; (d) an intrinsic base region (100), which is finer laterally than vertically, situated in contact with the intrinsic collector region and the emitter region supported on the vertical side of the first seat situated opposite a vertical side of the second seat; (e) an extrinsic base region (60) extending perpendicular to the intrinsic base region in the upper part of the separating zone; (f) some contact studs respectively situated in contact with the extrinsic collector, emitter and extrinsic base regions. The intrinsic base region is formed in a silicon-germanium alloy. Independent claims are also included for: (a) an integrated circuit incorporating such a transistor; (b) a method for the fabrication of the laterally functioning bipolar transistor.

    24.
    发明专利
    未知

    公开(公告)号：FR2819636A1

    公开(公告)日：2002-07-19

    申请号：FR0100418

    申请日：2001-01-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： MENUT OLIVIER ,  GRIS YVON

    IPC: H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/07

    Abstract: DRAM memory cell is made by forming an initial single crystal substrate having a trench capacitor that forms a crystal lattice discontinuity, amorphizing the lattice around periphery of a recess formed at the discontinuity, depositing amorphous material the same as that of initial substrate on obtained structure, thermally annealing, and forming an access transistor in contact with the trench. Fabrication of an integrated circuit comprising a semiconductor substrate (SB) supporting a DRAM memory cell comprising an access transistor (T) and a storage capacitor (TRC) comprises: (a) Producing an initial substrate having a local trench capacitor containing a polycrystalline filling material that emerges from the surface of the initial substrate and forms a discontinuity of the crystal lattice; (b) Forming a recess in the initial substrate at the level of the trench; (c) Amorphizing, locally and self-aligned on the trench, the single crystal lattice of the substrate at the periphery of the recess and the part of the filling material that emerges from the trench; (d) Depositing on the obtained structure a layer of amorphous material having the same chemical composition as that of the initial substrate; (e) Thermally annealing the obtained structure, in order to recrystallize the amorphous material so that it becomes continuous with the single crystal lattice of the initial substrate; and (f) Epitaxially growing an upper layer of the substrate, in and on which is produced an access transistor (T) whose source (S) or drain (D) region contacts the trench capacitor forming the storage capacitor (TRC) of the DRAM memory cell. The initial substrate production stage (a) involves successively depositing on the initial substrate a first layer of a first material and a second layer of a second material, and etching a trench, which is subsequently filled with a filling material. The recess forming stage (b) involves performing selective etching with respect to the second layer, the first layer and an upper part of the filling material of the trench, so as to form lateral cavities and a recess at the level of the single crystal discontinuity, and removing the second layer. The amorphization stage (c) involves localized ion implantation around the recess by using a mask. Either before or after stage (e), the surface of the structure is planarized, preferably by chemical-mechanical polishing. An Independent claim is given for an integrated circuit fabricated by the above process and supporting a DRAM memory cell comprising a transistor (T) and a storage capacitor (TRC).

    25.
    发明专利
    未知

    公开(公告)号：FR2819632A1

    公开(公告)日：2002-07-19

    申请号：FR0100419

    申请日：2001-01-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： MENUT OLIVIER ,  GRIS YVON

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: Sn one particular embodiment, the integrated circuit comprises a load storing semiconductor device comprising at least a control transistor T and a storage capacitor TRC. The device comprises a substrate including a lower region containing at least a buried capacitive trench TRC forming said storage capacitor, a casing CS located above said lower region of the substrate. The control transistor T is produced in and on the casing and said capacitive trench is located beneath the transistor and is in contact with the casing.

    COMPOSANT ELECTRONIQUE INTEGRANT UNE MATRICE DE CELLULES TCAM
    26.
    发明专利
    COMPOSANT ELECTRONIQUE INTEGRANT UNE MATRICE DE CELLULES TCAM 未知

    公开(公告)号：FR3006096A1

    公开(公告)日：2014-11-28

    申请号：FR1354714

    申请日：2013-05-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： MENUT OLIVIER ,  TURGIS DAVID ,  CIAMPOLINI LORENZO

    IPC: G11C15/04 ,  G11C11/401

    Abstract: Composant électronique incluant une mémoire adressable par contenu ternaire, configurée pour comparer les données d'entrée avec un ensemble de mots de données de référence préenregistrés, ladite mémoire comportant une matrice de cellules élémentaires (100, 200, 300, 400) disposée en lignes et colonnes, chaque ligne comportant des cellules dans chacune desquelles est enregistré un bit d'un des mots de données de référence, les cellules d'une même colonne étant dédiées à la comparaison de même bit du mot de données d'entrée, chaque cellule comportant : • deux points mémoire (102, 103) dans lesquels sont stockés des données représentatives du bit de données de référence ; • un circuit de comparaison (104, 204, 304, 404) connecté auxdits points mémoires et présentant un point de comparaison (150) dont le potentiel est représentatif de la comparaison du bit de la donnée d'entrée et des données stockées dans lesdits points mémoires, et comportant également un circuit commun de comparaison (50) auquel sont connectés les circuits de comparaison (104, 204, 304, 404) de tout ou partie des cellules d'une même colonne, ledit circuit de comparaison comportant des bornes (44, 47) sur lesquelles sont appliquées le bit du mot de données d'entrée (SL) et son complémentaire (/SL).

    CELLULE PRECARACTERISEE POUR CIRCUIT INTÉGRÉ
    28.
    发明专利
    CELLULE PRECARACTERISEE POUR CIRCUIT INTÉGRÉ 未知

    公开(公告)号：FR2968128A1

    公开(公告)日：2012-06-01

    申请号：FR1059777

    申请日：2010-11-26

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS INC

    Inventor： SENGUPTA RWIK ,  GUPTA ROHIT KUMAR ,  GOYAL MITESH ,  MENUT OLIVIER

    IPC: H01L23/50 ,  H01L23/535 ,  H01L29/72

    Abstract: La cellule précaractérisée comprend plusieurs lignes électriquement conductrices parallèles (LGi) s'étendant au dessus des première et deuxième régions (RG1, RG2) contenant des zones semiconductrices, et des contacts de lignes électriquement conducteurs (ZCi) électriquement couplés auxdites lignes ; la cellule (CEL) est réalisée dans une technologie CMOS inférieure à 28 nanomètres et les contacts de lignes (ZCi) comprennent un premier groupe d'au moins un premier contact de ligne (ZC1, ZC3) disposé entre la première région (RG1) et l'extrémité correspondante (BS1) de la cellule et un deuxième groupe d'au moins un deuxième contact de ligne (ZC2, ZC4) disposé entre la première région (RG1) et la deuxième région (RG2), deux lignes adjacentes (LG1, LG2) étant respectivement couplées à un premier contact de ligne (ZC1) et à un deuxième contact de ligne (ZC2).

    29.
    发明专利
    未知

    公开(公告)号：DE60216646D1

    公开(公告)日：2007-01-25

    申请号：DE60216646

    申请日：2002-01-09

    Applicant: ST MICROELECTRONICS SA

    Inventor： MENUT OLIVIER ,  GRIS YVON

    IPC: H01L21/76 ,  H01L21/762 ,  H01L21/20 ,  H01L21/205 ,  H01L21/329 ,  H01L21/822 ,  H01L27/04 ,  H01L29/861

    Abstract: Semiconductor single crystal substrate is made by forming an initial single crystal substrate (1) having lattice discontinuity locally on its surface, amorphizing the lattice around periphery of a recess formed at the discontinuity, depositing amorphous material the same as that of initial substrate on the obtained structure, and thermally annealing, to recrystallize the amorphous material. Production of a semiconductor single crystal substrate involves: (a) Forming an initial single crystal substrate (1), then successively depositing on the initial substrate (1) a first layer (2) of a first material and a second layer (3) of a second material, and etching a trench (4) which is subsequently filled with a filling material and which forms a lattice discontinuity in the single crystal lattice; (b) Performing selective etching with respect to the second layer (3), the first layer (2) and an upper part of the filling material of the trench (4), so as to form lateral cavities and a recess at the level of the single crystal discontinuity, and removing the second layer (3); (c) Amorphizing the single crystal lattice around the periphery of the recess; (d) Depositing a layer of amorphous material having the same chemical composition as that of the initial substrate (1) on the obtained structure; and (e) Thermally annealing the structure, in order to recrystallize the amorphous material so that it becomes continuous with the single crystal lattice of the initial substrate. The initial substrate is selected from silicon, germanium, silicon carbide, gallium arsenide, and an alloy containing at least some of these materials. The amorphization stage (c) involves localized ion implantation around the recess by using a mask. Amorphization is self-aligned on the trench (4). Either before or after stage (e), the surface of the structure is planarized, preferably by chemical-mechanical polishing. An Independent claim is given for an integrated circuit comprising a single crystal silicon substrate produced by the above process, and comprising at least two adjacent transistors produced in the body of the substrate that includes at least one buried trench forming an isolating trench separating the buried layers adjacent to the transistors.

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